rp: Run clang-format
This commit is contained in:
James Turton
Rachel Mant
parent
14882c61ab
commit
bf0302b076
260
src/target/rp.c
260
src/target/rp.c
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@ -56,19 +56,19 @@
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#define RP_SRAM_BASE 0x20000000U
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#define RP_SRAM_SIZE 0x42000U
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#define RP_GPIO_QSPI_BASE_ADDR 0x40018000U
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#define RP_GPIO_QSPI_SCLK_CTRL (RP_GPIO_QSPI_BASE_ADDR + 0x04U)
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#define RP_GPIO_QSPI_CS_CTRL (RP_GPIO_QSPI_BASE_ADDR + 0x0cU)
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#define RP_GPIO_QSPI_SD0_CTRL (RP_GPIO_QSPI_BASE_ADDR + 0x14U)
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#define RP_GPIO_QSPI_SD1_CTRL (RP_GPIO_QSPI_BASE_ADDR + 0x1cU)
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#define RP_GPIO_QSPI_SD2_CTRL (RP_GPIO_QSPI_BASE_ADDR + 0x24U)
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#define RP_GPIO_QSPI_SD3_CTRL (RP_GPIO_QSPI_BASE_ADDR + 0x2cU)
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#define RP_GPIO_QSPI_CS_DRIVE_NORMAL (0U << 8U)
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#define RP_GPIO_QSPI_CS_DRIVE_INVERT (1U << 8U)
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#define RP_GPIO_QSPI_CS_DRIVE_LOW (2U << 8U)
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#define RP_GPIO_QSPI_CS_DRIVE_HIGH (3U << 8U)
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#define RP_GPIO_QSPI_CS_DRIVE_MASK 0x00000300U
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#define RP_GPIO_QSPI_SD1_CTRL_INOVER_BITS 0x00030000U
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#define RP_GPIO_QSPI_BASE_ADDR 0x40018000U
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#define RP_GPIO_QSPI_SCLK_CTRL (RP_GPIO_QSPI_BASE_ADDR + 0x04U)
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#define RP_GPIO_QSPI_CS_CTRL (RP_GPIO_QSPI_BASE_ADDR + 0x0cU)
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#define RP_GPIO_QSPI_SD0_CTRL (RP_GPIO_QSPI_BASE_ADDR + 0x14U)
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#define RP_GPIO_QSPI_SD1_CTRL (RP_GPIO_QSPI_BASE_ADDR + 0x1cU)
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#define RP_GPIO_QSPI_SD2_CTRL (RP_GPIO_QSPI_BASE_ADDR + 0x24U)
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#define RP_GPIO_QSPI_SD3_CTRL (RP_GPIO_QSPI_BASE_ADDR + 0x2cU)
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#define RP_GPIO_QSPI_CS_DRIVE_NORMAL (0U << 8U)
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#define RP_GPIO_QSPI_CS_DRIVE_INVERT (1U << 8U)
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#define RP_GPIO_QSPI_CS_DRIVE_LOW (2U << 8U)
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#define RP_GPIO_QSPI_CS_DRIVE_HIGH (3U << 8U)
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#define RP_GPIO_QSPI_CS_DRIVE_MASK 0x00000300U
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#define RP_GPIO_QSPI_SD1_CTRL_INOVER_BITS 0x00030000U
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#define RP_SSI_BASE_ADDR 0x18000000U
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#define RP_SSI_CTRL0 (RP_SSI_BASE_ADDR + 0x00U)
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@ -93,40 +93,40 @@
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#define RP_SSI_CTRL0_TMOD_EEPROM (3U << 8U)
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#define RP_SSI_CTRL0_DATA_BIT_MASK 0x001f0000U
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#define RP_SSI_CTRL0_DATA_BIT_SHIFT 16U
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#define RP_SSI_CTRL0_DATA_BITS(x) (((x) - 1U) << RP_SSI_CTRL0_DATA_BIT_SHIFT)
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#define RP_SSI_CTRL0_DATA_BITS(x) (((x)-1U) << RP_SSI_CTRL0_DATA_BIT_SHIFT)
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#define RP_SSI_CTRL0_MASK (RP_SSI_CTRL0_FRF_MASK | RP_SSI_CTRL0_TMOD_MASK | RP_SSI_CTRL0_DATA_BIT_MASK)
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#define RP_SSI_ENABLE_SSI (1U << 0U)
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#define RP_SSI_XIP_SPI_CTRL0_FORMAT_STD_SPI (0U << 0U)
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#define RP_SSI_XIP_SPI_CTRL0_FORMAT_SPLIT (1U << 0U)
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#define RP_SSI_XIP_SPI_CTRL0_FORMAT_FRF (2U << 0U)
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#define RP_SSI_XIP_SPI_CTRL0_ADDRESS_LENGTH(x) (((x) * 2U) << 2U)
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#define RP_SSI_XIP_SPI_CTRL0_ADDRESS_LENGTH(x) (((x)*2U) << 2U)
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#define RP_SSI_XIP_SPI_CTRL0_INSTR_LENGTH_8b (2U << 8U)
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#define RP_SSI_XIP_SPI_CTRL0_WAIT_CYCLES(x) (((x) * 8U) << 11U)
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#define RP_SSI_XIP_SPI_CTRL0_WAIT_CYCLES(x) (((x)*8U) << 11U)
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#define RP_SSI_XIP_SPI_CTRL0_XIP_CMD_SHIFT 24U
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#define RP_SSI_XIP_SPI_CTRL0_XIP_CMD(x) ((x) << RP_SSI_XIP_SPI_CTRL0_XIP_CMD_SHIFT)
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#define RP_SSI_XIP_SPI_CTRL0_TRANS_1C1A (0U << 0U)
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#define RP_SSI_XIP_SPI_CTRL0_TRANS_1C2A (1U << 0U)
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#define RP_SSI_XIP_SPI_CTRL0_TRANS_2C2A (2U << 0U)
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#define RP_PADS_QSPI_BASE_ADDR 0x40020000U
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#define RP_PADS_QSPI_GPIO_SD0 (RP_PADS_QSPI_BASE_ADDR + 0x08U)
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#define RP_PADS_QSPI_GPIO_SD1 (RP_PADS_QSPI_BASE_ADDR + 0x0cU)
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#define RP_PADS_QSPI_GPIO_SD2 (RP_PADS_QSPI_BASE_ADDR + 0x10U)
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#define RP_PADS_QSPI_GPIO_SD3 (RP_PADS_QSPI_BASE_ADDR + 0x14U)
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#define RP_PADS_QSPI_GPIO_SD0_OD_BITS 0x00000080U
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#define RP_PADS_QSPI_GPIO_SD0_PUE_BITS 0x00000008U
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#define RP_PADS_QSPI_GPIO_SD0_PDE_BITS 0x00000004U
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#define RP_PADS_QSPI_BASE_ADDR 0x40020000U
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#define RP_PADS_QSPI_GPIO_SD0 (RP_PADS_QSPI_BASE_ADDR + 0x08U)
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#define RP_PADS_QSPI_GPIO_SD1 (RP_PADS_QSPI_BASE_ADDR + 0x0cU)
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#define RP_PADS_QSPI_GPIO_SD2 (RP_PADS_QSPI_BASE_ADDR + 0x10U)
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#define RP_PADS_QSPI_GPIO_SD3 (RP_PADS_QSPI_BASE_ADDR + 0x14U)
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#define RP_PADS_QSPI_GPIO_SD0_OD_BITS 0x00000080U
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#define RP_PADS_QSPI_GPIO_SD0_PUE_BITS 0x00000008U
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#define RP_PADS_QSPI_GPIO_SD0_PDE_BITS 0x00000004U
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#define RP_XIP_BASE_ADDR 0x14000000U
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#define RP_XIP_CTRL (RP_XIP_BASE_ADDR + 0x00U)
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#define RP_XIP_FLUSH (RP_XIP_BASE_ADDR + 0x04U)
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#define RP_XIP_CTRL_ENABLE 0x00000001U
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#define RP_XIP_BASE_ADDR 0x14000000U
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#define RP_XIP_CTRL (RP_XIP_BASE_ADDR + 0x00U)
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#define RP_XIP_FLUSH (RP_XIP_BASE_ADDR + 0x04U)
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#define RP_XIP_CTRL_ENABLE 0x00000001U
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#define RP_RESETS_BASE_ADDR 0x4000c000U
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#define RP_RESETS_RESET (RP_RESETS_BASE_ADDR + 0x00U)
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#define RP_RESETS_RESET_DONE (RP_RESETS_BASE_ADDR + 0x08U)
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#define RP_RESETS_RESET_IO_QSPI_BITS 0x00000040U
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#define RP_RESETS_RESET_PADS_QSPI_BITS 0x00000200U
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#define RP_RESETS_BASE_ADDR 0x4000c000U
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#define RP_RESETS_RESET (RP_RESETS_BASE_ADDR + 0x00U)
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#define RP_RESETS_RESET_DONE (RP_RESETS_BASE_ADDR + 0x08U)
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#define RP_RESETS_RESET_IO_QSPI_BITS 0x00000040U
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#define RP_RESETS_RESET_PADS_QSPI_BITS 0x00000200U
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#define BOOTROM_FUNC_TABLE_ADDR 0x00000014U
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#define BOOTROM_FUNC_TABLE_TAG(x, y) ((uint8_t)(x) | ((uint8_t)(y) << 8U))
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@ -142,7 +142,7 @@
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#define RP_SPI_OPCODE(x) (x)
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#define RP_SPI_OPCODE_MASK 0x00ffU
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#define RP_SPI_INTER_SHIFT 8U
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#define RP_SPI_INTER_LENGTH(x) (((x) & 7U) << RP_SPI_INTER_SHIFT)
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#define RP_SPI_INTER_LENGTH(x) (((x)&7U) << RP_SPI_INTER_SHIFT)
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#define RP_SPI_INTER_MASK 0x0700U
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#define RP_SPI_FRAME_OPCODE_ONLY (1 << 11U)
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#define RP_SPI_FRAME_OPCODE_3B_ADDR (2 << 11U)
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@ -157,9 +157,9 @@
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*/
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#define SPI_FLASH_CMD_SECTOR_ERASE 0x20
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#define FLASHCMD_BLOCK32K_ERASE 0x52
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#define FLASHCMD_BLOCK64K_ERASE 0xd8
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#define FLASHCMD_CHIP_ERASE 0x60
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#define FLASHCMD_BLOCK32K_ERASE 0x52
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#define FLASHCMD_BLOCK64K_ERASE 0xd8
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#define FLASHCMD_CHIP_ERASE 0x60
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#define SPI_FLASH_CMD_READ_JEDEC_ID (RP_SPI_OPCODE(0x9fU) | RP_SPI_INTER_LENGTH(0) | RP_SPI_FRAME_OPCODE_ONLY)
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#define SPI_FLASH_CMD_READ_SFDP (RP_SPI_OPCODE(0x5aU) | RP_SPI_INTER_LENGTH(1) | RP_SPI_FRAME_OPCODE_3B_ADDR)
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@ -205,9 +205,9 @@ static uint32_t rp_get_flash_length(target *t);
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static bool rp_mass_erase(target *t);
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// Our own implementation of bootloader functions for handling flash chip
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static void __attribute__((unused))rp_flash_connect_internal(target *t);
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static void __attribute__((unused)) rp_flash_connect_internal(target *t);
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static void rp_flash_exit_xip(target *t);
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static void __attribute__((unused))rp_flash_flush_cache(target *t);
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static void __attribute__((unused)) rp_flash_flush_cache(target *t);
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static void rp_flash_enter_xip(target *t);
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static void rp_spi_read_sfdp(target *const t, const uint32_t address, void *const buffer, const size_t length)
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@ -622,14 +622,15 @@ static void rp_spi_read(
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// Connect the XIP controller to the flash pads
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static void rp_flash_connect_internal(target *t)
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{
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// Use hard reset to force IO and pad controls to known state (don't touch
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// IO_BANK0 as that does not affect XIP signals)
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// Use hard reset to force IO and pad controls to known state (don't touch
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// IO_BANK0 as that does not affect XIP signals)
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uint32_t reset = target_mem_read32(t, RP_RESETS_RESET);
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target_mem_write32(t, RP_RESETS_RESET, reset | RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS);
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target_mem_write32(t, RP_RESETS_RESET, reset);
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while (~target_mem_read32(t, RP_RESETS_RESET_DONE) & (RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS));
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target_mem_write32(t, RP_RESETS_RESET, reset | RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS);
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target_mem_write32(t, RP_RESETS_RESET, reset);
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while (
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~target_mem_read32(t, RP_RESETS_RESET_DONE) & (RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS));
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// Then mux XIP block onto internal QSPI flash pads
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// Then mux XIP block onto internal QSPI flash pads
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target_mem_write32(t, RP_GPIO_QSPI_SCLK_CTRL, 0);
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target_mem_write32(t, RP_GPIO_QSPI_CS_CTRL, 0);
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target_mem_write32(t, RP_GPIO_QSPI_SD0_CTRL, 0);
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@ -652,9 +653,9 @@ static void rp_flash_init_spi(target *t)
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// Hopefully-conservative baud rate for boot and programming
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target_mem_write32(t, RP_SSI_BAUD, 6);
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target_mem_write32(t, RP_SSI_CTRL0,
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RP_SSI_CTRL0_FRF_SERIAL | // Standard 1-bit SPI serial frames
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RP_SSI_CTRL0_DATA_BITS(8) | // 8 clocks per data frame
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RP_SSI_CTRL0_TMOD_BIDI // TX and RX FIFOs are both used for every byte
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RP_SSI_CTRL0_FRF_SERIAL | // Standard 1-bit SPI serial frames
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RP_SSI_CTRL0_DATA_BITS(8) | // 8 clocks per data frame
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RP_SSI_CTRL0_TMOD_BIDI // TX and RX FIFOs are both used for every byte
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);
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// Slave selected when transfers in progress
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target_mem_write32(t, RP_SSI_SER, 1);
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@ -664,8 +665,9 @@ static void rp_flash_init_spi(target *t)
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// Also allow any unbounded loops to check whether the above abort condition
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// was asserted, and terminate early
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static int rp_flash_was_aborted(target *t) {
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return target_mem_read32(t, RP_GPIO_QSPI_SD1_CTRL) & RP_GPIO_QSPI_SD1_CTRL_INOVER_BITS;
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static int rp_flash_was_aborted(target *t)
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{
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return target_mem_read32(t, RP_GPIO_QSPI_SD1_CTRL) & RP_GPIO_QSPI_SD1_CTRL_INOVER_BITS;
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}
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// Put bytes from one buffer, and get bytes into another buffer.
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@ -676,39 +678,40 @@ static int rp_flash_was_aborted(target *t) {
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// If rx_skip is nonzero, this many bytes will first be consumed from the FIFO,
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// before reading a further count bytes into *rx.
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// E.g. if you have written a command+address just before calling this function.
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static void rp_flash_put_get(target *t, const uint8_t *tx, uint8_t *rx, size_t count, size_t rx_skip) {
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// Make sure there is never more data in flight than the depth of the RX
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// FIFO. Otherwise, when we are interrupted for long periods, hardware
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// will overflow the RX FIFO.
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const uint max_in_flight = 16 - 2; // account for data internal to SSI
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size_t tx_count = count;
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size_t rx_count = count;
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while (tx_count || rx_skip || rx_count) {
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// NB order of reads, for pessimism rather than optimism
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uint32_t tx_level = target_mem_read32(t, RP_SSI_TXFLR);
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uint32_t rx_level = target_mem_read32(t, RP_SSI_RXFLR);
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bool did_something = false; // Expect this to be folded into control flow, not register
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if (tx_count && tx_level + rx_level < max_in_flight) {
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target_mem_write32(t, RP_SSI_DR0, (uint32_t) (tx ? *tx++ : 0));
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--tx_count;
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did_something = true;
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}
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if (rx_level) {
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uint8_t rxbyte = target_mem_read32(t, RP_SSI_DR0);
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did_something = true;
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if (rx_skip) {
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--rx_skip;
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} else {
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if (rx)
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*rx++ = rxbyte;
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--rx_count;
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}
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}
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// APB load costs 4 cycles, so only do it on idle loops (our budget is 48 cyc/byte)
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if (!did_something && rp_flash_was_aborted(t))
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break;
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}
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rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_HIGH);
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static void rp_flash_put_get(target *t, const uint8_t *tx, uint8_t *rx, size_t count, size_t rx_skip)
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{
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// Make sure there is never more data in flight than the depth of the RX
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// FIFO. Otherwise, when we are interrupted for long periods, hardware
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// will overflow the RX FIFO.
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const uint max_in_flight = 16 - 2; // account for data internal to SSI
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size_t tx_count = count;
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size_t rx_count = count;
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while (tx_count || rx_skip || rx_count) {
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// NB order of reads, for pessimism rather than optimism
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uint32_t tx_level = target_mem_read32(t, RP_SSI_TXFLR);
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uint32_t rx_level = target_mem_read32(t, RP_SSI_RXFLR);
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bool did_something = false; // Expect this to be folded into control flow, not register
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if (tx_count && tx_level + rx_level < max_in_flight) {
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target_mem_write32(t, RP_SSI_DR0, (uint32_t)(tx ? *tx++ : 0));
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--tx_count;
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did_something = true;
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}
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if (rx_level) {
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uint8_t rxbyte = target_mem_read32(t, RP_SSI_DR0);
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did_something = true;
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if (rx_skip) {
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--rx_skip;
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} else {
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if (rx)
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*rx++ = rxbyte;
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--rx_count;
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}
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}
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// APB load costs 4 cycles, so only do it on idle loops (our budget is 48 cyc/byte)
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if (!did_something && rp_flash_was_aborted(t))
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break;
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}
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rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_HIGH);
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}
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// Sequence:
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@ -721,55 +724,50 @@ static void rp_flash_put_get(target *t, const uint8_t *tx, uint8_t *rx, size_t c
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// Parts 1 and 2 are to improve compatibility with Micron parts
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static void rp_flash_exit_xip(target *t)
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{
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uint8_t buf[2];
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buf[0] = 0xff;
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buf[1] = 0xff;
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uint8_t buf[2];
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buf[0] = 0xff;
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buf[1] = 0xff;
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rp_flash_init_spi(t);
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uint32_t padctrl_save = target_mem_read32(t, RP_PADS_QSPI_GPIO_SD0);
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uint32_t padctrl_tmp = (padctrl_save
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& ~(RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PUE_BITS |
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RP_PADS_QSPI_GPIO_SD0_PDE_BITS)
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) | RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PDE_BITS;
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uint32_t padctrl_tmp = (padctrl_save & ~(RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PUE_BITS |
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RP_PADS_QSPI_GPIO_SD0_PDE_BITS)) |
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RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PDE_BITS;
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// First two 32-clock sequences
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// CSn is held high for the first 32 clocks, then asserted low for next 32
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rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_HIGH);
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for (int i = 0; i < 2; ++i) {
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// This gives 4 16-bit offset store instructions. Anything else seems to
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// produce a large island of constants
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD0, padctrl_tmp);
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD1, padctrl_tmp);
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD2, padctrl_tmp);
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD3, padctrl_tmp);
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// First two 32-clock sequences
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// CSn is held high for the first 32 clocks, then asserted low for next 32
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rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_HIGH);
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for (int i = 0; i < 2; ++i) {
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// This gives 4 16-bit offset store instructions. Anything else seems to
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// produce a large island of constants
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD0, padctrl_tmp);
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD1, padctrl_tmp);
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD2, padctrl_tmp);
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD3, padctrl_tmp);
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// Brief delay (~6000 cyc) for pulls to take effect
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// Brief delay (~6000 cyc) for pulls to take effect
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platform_delay(10);
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rp_flash_put_get(t, NULL, NULL, 4, 0);
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rp_flash_put_get(t, NULL, NULL, 4, 0);
|
||||
|
||||
padctrl_tmp = (padctrl_tmp
|
||||
& ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS)
|
||||
| RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
|
||||
padctrl_tmp = (padctrl_tmp & ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS) | RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
|
||||
|
||||
rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_LOW);
|
||||
}
|
||||
rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_LOW);
|
||||
}
|
||||
|
||||
// Restore IO/pad controls, and send 0xff, 0xff. Put pullup on IO2/IO3 as
|
||||
// these may be used as WPn/HOLDn at this point, and we are now starting
|
||||
// to issue serial commands.
|
||||
// Restore IO/pad controls, and send 0xff, 0xff. Put pullup on IO2/IO3 as
|
||||
// these may be used as WPn/HOLDn at this point, and we are now starting
|
||||
// to issue serial commands.
|
||||
|
||||
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD0, padctrl_save);
|
||||
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD1, padctrl_save);
|
||||
padctrl_save = (padctrl_save
|
||||
& ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS
|
||||
) | RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
|
||||
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD2, padctrl_save);
|
||||
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD3, padctrl_save);
|
||||
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD0, padctrl_save);
|
||||
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD1, padctrl_save);
|
||||
padctrl_save = (padctrl_save & ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS) | RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
|
||||
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD2, padctrl_save);
|
||||
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD3, padctrl_save);
|
||||
|
||||
rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_LOW);
|
||||
rp_flash_put_get(t, buf, NULL, 2, 0);
|
||||
rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_LOW);
|
||||
rp_flash_put_get(t, buf, NULL, 2, 0);
|
||||
|
||||
target_mem_write32(t, RP_GPIO_QSPI_CS_CTRL, 0);
|
||||
}
|
||||
|
|
@ -780,13 +778,13 @@ static void rp_flash_exit_xip(target *t)
|
|||
// programming.
|
||||
static void rp_flash_flush_cache(target *t)
|
||||
{
|
||||
target_mem_write32(t, RP_XIP_FLUSH, 1);
|
||||
// Read blocks until flush completion
|
||||
target_mem_read32(t, RP_XIP_FLUSH);
|
||||
// Enable the cache
|
||||
target_mem_write32(t, RP_XIP_FLUSH, 1);
|
||||
// Read blocks until flush completion
|
||||
target_mem_read32(t, RP_XIP_FLUSH);
|
||||
// Enable the cache
|
||||
const uint32_t ctrl = target_mem_read32(t, RP_XIP_CTRL);
|
||||
target_mem_write32(t, RP_XIP_CTRL, ctrl | RP_XIP_CTRL_ENABLE);
|
||||
rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_NORMAL);
|
||||
rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_NORMAL);
|
||||
}
|
||||
|
||||
// Put the SSI into a mode where XIP accesses translate to standard
|
||||
|
|
@ -796,15 +794,15 @@ static void rp_flash_enter_xip(target *t)
|
|||
{
|
||||
target_mem_write32(t, RP_SSI_ENABLE, 0);
|
||||
target_mem_write32(t, RP_SSI_CTRL0,
|
||||
RP_SSI_CTRL0_FRF_SERIAL | // Standard 1-bit SPI serial frames
|
||||
RP_SSI_CTRL0_DATA_BITS(32) | // 32 clocks per data frame
|
||||
RP_SSI_CTRL0_TMOD_EEPROM // Send instr + addr, receive data
|
||||
RP_SSI_CTRL0_FRF_SERIAL | // Standard 1-bit SPI serial frames
|
||||
RP_SSI_CTRL0_DATA_BITS(32) | // 32 clocks per data frame
|
||||
RP_SSI_CTRL0_TMOD_EEPROM // Send instr + addr, receive data
|
||||
);
|
||||
target_mem_write32(t, RP_SSI_XIP_SPI_CTRL0,
|
||||
RP_SSI_XIP_SPI_CTRL0_XIP_CMD(0x03) | // Standard 03h read
|
||||
RP_SSI_XIP_SPI_CTRL0_INSTR_LENGTH_8b | // 8-bit instruction prefix
|
||||
RP_SSI_XIP_SPI_CTRL0_ADDRESS_LENGTH(0x03) | // 24-bit addressing for 03h commands
|
||||
RP_SSI_XIP_SPI_CTRL0_TRANS_1C1A // Command and address both in serial format
|
||||
RP_SSI_XIP_SPI_CTRL0_XIP_CMD(0x03) | // Standard 03h read
|
||||
RP_SSI_XIP_SPI_CTRL0_INSTR_LENGTH_8b | // 8-bit instruction prefix
|
||||
RP_SSI_XIP_SPI_CTRL0_ADDRESS_LENGTH(0x03) | // 24-bit addressing for 03h commands
|
||||
RP_SSI_XIP_SPI_CTRL0_TRANS_1C1A // Command and address both in serial format
|
||||
);
|
||||
target_mem_write32(t, RP_SSI_ENABLE, RP_SSI_ENABLE_SSI);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue