First cut at an Atmel SAM3X driver.
This commit is contained in:
Gareth McMullin
parent
33905d7203
commit
c09cbe8719
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@ -29,6 +29,7 @@ SRC = gdb_if.c \
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arm7tdmi.c \
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stm32f4.c \
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crc32.c \
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sam3x.c \
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include $(PLATFORM_DIR)/Makefile.inc
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@ -326,11 +326,12 @@ cortexm_probe(struct target_s *target)
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#define PROBE(x) \
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do { if (!(x)(target) && !target_check_error(target)) return 0; } while (0)
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do { if (!(x)(target)) return 0; else target_check_error(target); } while (0)
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PROBE(stm32f1_probe);
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PROBE(stm32f4_probe);
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PROBE(lpc11xx_probe);
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PROBE(sam3x_probe);
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/* Try LMI last, as it doesn't fail. */
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PROBE(lmi_probe);
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#undef PROBE
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@ -161,6 +161,7 @@ typedef struct target_s {
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/* target-defined options */
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unsigned target_options;
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uint32_t idcode;
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/* Flash memory access functions */
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const char *xml_mem_map;
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@ -184,6 +185,7 @@ int stm32f1_probe(struct target_s *target);
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int stm32f4_probe(struct target_s *target);
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int lmi_probe(struct target_s *target);
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int lpc11xx_probe(struct target_s *target);
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int sam3x_probe(struct target_s *target);
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#endif
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@ -0,0 +1,221 @@
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/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2012 Black Sphere Technologies Ltd.
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* Written by Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements Atmel SAM3X target specific functions for detecting
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* the device, providing the XML memory map and Flash memory programming.
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*/
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#include <stdlib.h>
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#include <string.h>
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#include "general.h"
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#include "adiv5.h"
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#include "target.h"
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static int sam3x_flash_erase(struct target_s *target, uint32_t addr, int len);
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static int sam3x_flash_write(struct target_s *target, uint32_t dest,
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const uint8_t *src, int len);
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static const char sam3x_driver_str[] = "Atmel SAM3X";
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static const char sam3x_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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/* "<!DOCTYPE memory-map "
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" PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
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" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"*/
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"<memory-map>"
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" <memory type=\"flash\" start=\"0x80000\" length=\"0x80000\">"
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" <property name=\"blocksize\">0x100</property>"
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" </memory>"
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" <memory type=\"rom\" start=\"0x100000\" length=\"0x200000\"/>"
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" <memory type=\"ram\" start=\"0x20000000\" length=\"0x200000\"/>"
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"</memory-map>";
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/* Enhanced Embedded Flash Controller (EEFC) Register Map */
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#define EEFC_BASE(x) (0x400E0A00+((x)*0x400))
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#define EEFC_FMR(x) (EEFC_BASE(x)+0x00)
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#define EEFC_FCR(x) (EEFC_BASE(x)+0x04)
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#define EEFC_FSR(x) (EEFC_BASE(x)+0x08)
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#define EEFC_FRR(x) (EEFC_BASE(x)+0x0C)
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#define EEFC_FCR_FKEY (0x5A << 24)
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#define EEFC_FCR_FCMD_GETD 0x00
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#define EEFC_FCR_FCMD_WP 0x01
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#define EEFC_FCR_FCMD_WPL 0x02
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#define EEFC_FCR_FCMD_EWP 0x03
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#define EEFC_FCR_FCMD_EWPL 0x04
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#define EEFC_FCR_FCMD_EA 0x05
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#define EEFC_FCR_FCMD_SLB 0x08
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#define EEFC_FCR_FCMD_CLB 0x09
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#define EEFC_FCR_FCMD_GLB 0x0A
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#define EEFC_FCR_FCMD_SGPB 0x0B
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#define EEFC_FCR_FCMD_CGPB 0x0C
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#define EEFC_FCR_FCMD_GGPB 0x0D
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#define EEFC_FCR_FCMD_STUI 0x0E
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#define EEFC_FCR_FCMD_SPUI 0x0F
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#define EEFC_FSR_FRDY (1 << 0)
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#define EEFC_FSR_FCMDE (1 << 1)
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#define EEFC_FSR_FLOCKE (1 << 2)
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#define EEFC_FSR_ERROR (EEFC_FSR_FCMDE | EEFC_FSR_FLOCKE)
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#define CHIPID_CIDR 0x400E0940
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#define CHIPID_CIDR_VERSION_MASK (0x1F << 0)
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#define CHIPID_CIDR_EPROC_CM3 (0x03 << 5)
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#define CHIPID_CIDR_EPROC_MASK (0x07 << 5)
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#define CHIPID_CIDR_NVPSIZ_MASK (0x0F << 8)
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#define CHIPID_CIDR_NVPSIZ_128K (0x07 << 8)
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#define CHIPID_CIDR_NVPSIZ_256K (0x09 << 8)
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#define CHIPID_CIDR_NVPSIZ_512K (0x0A << 8)
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#define CHIPID_CIDR_NVPSIZ2_MASK (0x0F << 12)
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#define CHIPID_CIDR_SRAMSIZ_MASK (0x0F << 16)
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#define CHIPID_CIDR_ARCH_MASK (0xFF << 20)
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#define CHIPID_CIDR_ARCH_SAM3XxC (0x84 << 20)
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#define CHIPID_CIDR_ARCH_SAM3XxE (0x85 << 20)
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#define CHIPID_CIDR_ARCH_SAM3XxG (0x86 << 20)
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#define CHIPID_CIDR_NVPTYP_MASK (0x07 << 28)
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#define CHIPID_CIDR_NVPTYP_FLASH (0x02 << 28)
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#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x03 << 28)
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#define CHIPID_CIDR_EXT (0x01 << 31)
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#define PAGE_SIZE 256
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int sam3x_probe(struct target_s *target)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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target->idcode = adiv5_ap_mem_read(ap, CHIPID_CIDR);
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/* FIXME: Check for all variants with similar flash interface */
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switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) {
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case CHIPID_CIDR_ARCH_SAM3XxC | CHIPID_CIDR_EPROC_CM3:
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case CHIPID_CIDR_ARCH_SAM3XxE | CHIPID_CIDR_EPROC_CM3:
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case CHIPID_CIDR_ARCH_SAM3XxG | CHIPID_CIDR_EPROC_CM3:
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target->driver = sam3x_driver_str;
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target->xml_mem_map = sam3x_xml_memory_map;
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target->flash_erase = sam3x_flash_erase;
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target->flash_write = sam3x_flash_write;
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return 0;
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}
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return -1;
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}
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static int
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sam3x_flash_cmd(struct target_s *target, int bank, uint8_t cmd, uint16_t arg)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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adiv5_ap_mem_write(ap, EEFC_FCR(bank),
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EEFC_FCR_FKEY | cmd | ((uint32_t)arg << 8));
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while(!(adiv5_ap_mem_read(ap, EEFC_FSR(bank)) & EEFC_FSR_FRDY))
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if(target_check_error(target))
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return -1;
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uint32_t sr = adiv5_ap_mem_read(ap, EEFC_FSR(bank));
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return sr & EEFC_FSR_ERROR;
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}
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static int
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sam3x_flash_bank(struct target_s *target, uint32_t addr, uint32_t *offset)
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{
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uint32_t half = -1;
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switch (target->idcode & CHIPID_CIDR_NVPSIZ_MASK) {
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case CHIPID_CIDR_NVPSIZ_128K:
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half = 0x00090000;
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break;
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case CHIPID_CIDR_NVPSIZ_256K:
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half = 0x000A0000;
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break;
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case CHIPID_CIDR_NVPSIZ_512K:
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half = 0x000C0000;
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break;
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}
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if (addr > half) {
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if (offset)
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*offset = addr - half;
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return 1;
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}
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if (offset)
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*offset = addr - 0x80000;
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return 0;
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}
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static int sam3x_flash_erase(struct target_s *target, uint32_t addr, int len)
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{
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/* FIXME: This device can't do sector erase. What do we do here?
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* Sector erase is done as part of write cycle in sam3x_flash_write()
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*/
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(void)target;
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(void)addr;
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(void)len;
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return 0;
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}
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static int sam3x_flash_write(struct target_s *target, uint32_t dest,
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const uint8_t *src, int len)
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{
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uint32_t offset;
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uint8_t bank = sam3x_flash_bank(target, dest, &offset);
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uint32_t buf[PAGE_SIZE];
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unsigned first_chunk = offset / PAGE_SIZE;
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unsigned last_chunk = (offset + len - 1) / PAGE_SIZE;
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offset %= PAGE_SIZE;
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dest -= offset;
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for (unsigned chunk = first_chunk; chunk <= last_chunk; chunk++) {
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DEBUG("chunk %u len %d\n", chunk, len);
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/* first and last chunk may require special handling */
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if ((chunk == first_chunk) || (chunk == last_chunk)) {
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/* fill with all ff to avoid sector rewrite corrupting other writes */
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memset(buf, 0xff, sizeof(buf));
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/* copy as much as fits */
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int copylen = PAGE_SIZE - offset;
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if (copylen > len)
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copylen = len;
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memcpy(&buf[offset], src, copylen);
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/* update to suit */
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len -= copylen;
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src += copylen;
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offset = 0;
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} else {
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/* interior chunk, must be aligned and full-sized */
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memcpy(buf, src, PAGE_SIZE);
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len -= PAGE_SIZE;
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src += PAGE_SIZE;
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}
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target_mem_write_words(target, dest, buf, PAGE_SIZE);
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if(sam3x_flash_cmd(target, bank, EEFC_FCR_FCMD_EWP, chunk))
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return -1;
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}
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return 0;
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}
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