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Improve cortexm_read/write_regs. Use more sensible return types.

This commit is contained in:
Gareth McMullin 2015-03-29 17:37:03 -07:00
parent 274b818517
commit c2cde32716
3 changed files with 26 additions and 31 deletions
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7
src/adiv5.c
View File

@ -37,7 +37,7 @@
static const char adiv5_driver_str[] = "ARM ADIv5 MEM-AP"; static const char adiv5_driver_str[] = "ARM ADIv5 MEM-AP";
static int ap_check_error(target *t); static bool ap_check_error(target *t);
static void ap_mem_read(target *t, void *dest, uint32_t src, size_t len); static void ap_mem_read(target *t, void *dest, uint32_t src, size_t len);
static void ap_mem_write(target *t, uint32_t dest, const void *src, size_t len); static void ap_mem_write(target *t, uint32_t dest, const void *src, size_t len);
@ -157,11 +157,10 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
adiv5_dp_unref(dp); adiv5_dp_unref(dp);
} }
static int static bool ap_check_error(target *t)
ap_check_error(target *t)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(t); ADIv5_AP_t *ap = adiv5_target_ap(t);
return adiv5_dp_error(ap->dp); return adiv5_dp_error(ap->dp) != 0;
} }
enum align { enum align {

46
src/cortexm.c
View File

@ -57,8 +57,8 @@ const struct command_s cortexm_cmd_list[] = {
#define SIGSEGV 11 #define SIGSEGV 11
#define SIGLOST 29 #define SIGLOST 29
static int cortexm_regs_read(target *t, void *data); static void cortexm_regs_read(target *t, void *data);
static int cortexm_regs_write(target *t, const void *data); static void cortexm_regs_write(target *t, const void *data);
static uint32_t cortexm_pc_read(target *t); static uint32_t cortexm_pc_read(target *t);
static void cortexm_reset(target *t); static void cortexm_reset(target *t);
@ -343,15 +343,16 @@ void cortexm_detach(target *t)
target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY); target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY);
} }
static int cortexm_regs_read(target *t, void *data) enum { DB_DHCSR, DB_DCRSR, DB_DCRDR, DB_DEMCR };
static void cortexm_regs_read(target *t, void *data)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(t); ADIv5_AP_t *ap = adiv5_target_ap(t);
uint32_t *regs = data; uint32_t *regs = data;
unsigned i; unsigned i;
/* FIXME: Describe what's really going on here */ /* FIXME: Describe what's really going on here */
adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD);
ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE);
/* Map the banked data registers (0x10-0x1c) to the /* Map the banked data registers (0x10-0x1c) to the
* debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */ * debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */
@ -359,33 +360,30 @@ static int cortexm_regs_read(target *t, void *data)
/* Walk the regnum_cortex_m array, reading the registers it /* Walk the regnum_cortex_m array, reading the registers it
* calls out. */ * calls out. */
adiv5_ap_write(ap, ADIV5_AP_DB(1), regnum_cortex_m[0]); /* Required to switch banks */ adiv5_ap_write(ap, ADIV5_AP_DB(DB_DCRSR), regnum_cortex_m[0]); /* Required to switch banks */
*regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(2)); *regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(DB_DCRDR));
for(i = 1; i < sizeof(regnum_cortex_m) / 4; i++) { for(i = 1; i < sizeof(regnum_cortex_m) / 4; i++) {
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(1), adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRSR),
regnum_cortex_m[i]); regnum_cortex_m[i]);
*regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(2)); *regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(DB_DCRDR));
} }
if (t->target_options & TOPT_FLAVOUR_V7MF) if (t->target_options & TOPT_FLAVOUR_V7MF)
for(i = 0; i < sizeof(regnum_cortex_mf) / 4; i++) { for(i = 0; i < sizeof(regnum_cortex_mf) / 4; i++) {
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE,
ADIV5_AP_DB(1), ADIV5_AP_DB(DB_DCRSR),
regnum_cortex_mf[i]); regnum_cortex_mf[i]);
*regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(2)); *regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(DB_DCRDR));
}
} }
return 0; static void cortexm_regs_write(target *t, const void *data)
}
static int cortexm_regs_write(target *t, const void *data)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(t); ADIv5_AP_t *ap = adiv5_target_ap(t);
const uint32_t *regs = data; const uint32_t *regs = data;
unsigned i; unsigned i;
/* FIXME: Describe what's really going on here */ /* FIXME: Describe what's really going on here */
adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD);
ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE);
/* Map the banked data registers (0x10-0x1c) to the /* Map the banked data registers (0x10-0x1c) to the
* debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */ * debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */
@ -393,25 +391,23 @@ static int cortexm_regs_write(target *t, const void *data)
/* Walk the regnum_cortex_m array, writing the registers it /* Walk the regnum_cortex_m array, writing the registers it
* calls out. */ * calls out. */
adiv5_ap_write(ap, ADIV5_AP_DB(2), *regs++); /* Required to switch banks */ adiv5_ap_write(ap, ADIV5_AP_DB(DB_DCRDR), *regs++); /* Required to switch banks */
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(1), adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRSR),
0x10000 | regnum_cortex_m[0]); 0x10000 | regnum_cortex_m[0]);
for(i = 1; i < sizeof(regnum_cortex_m) / 4; i++) { for(i = 1; i < sizeof(regnum_cortex_m) / 4; i++) {
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE,
ADIV5_AP_DB(2), *regs++); ADIV5_AP_DB(DB_DCRDR), *regs++);
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(1), adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRSR),
0x10000 | regnum_cortex_m[i]); 0x10000 | regnum_cortex_m[i]);
} }
if (t->target_options & TOPT_FLAVOUR_V7MF) if (t->target_options & TOPT_FLAVOUR_V7MF)
for(i = 0; i < sizeof(regnum_cortex_mf) / 4; i++) { for(i = 0; i < sizeof(regnum_cortex_mf) / 4; i++) {
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE,
ADIV5_AP_DB(2), *regs++); ADIV5_AP_DB(DB_DCRDR), *regs++);
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE,
ADIV5_AP_DB(1), ADIV5_AP_DB(DB_DCRSR),
0x10000 | regnum_cortex_mf[i]); 0x10000 | regnum_cortex_mf[i]);
} }
return 0;
} }
static uint32_t cortexm_pc_read(target *t) static uint32_t cortexm_pc_read(target *t)

6
src/include/target.h
View File

@ -115,7 +115,7 @@ struct target_s {
/* Attach/Detach funcitons */ /* Attach/Detach funcitons */
bool (*attach)(target *t); bool (*attach)(target *t);
void (*detach)(target *t); void (*detach)(target *t);
int (*check_error)(target *t); bool (*check_error)(target *t);
/* Memory access functions */ /* Memory access functions */
void (*mem_read)(target *t, void *dest, uint32_t src, void (*mem_read)(target *t, void *dest, uint32_t src,
@ -126,8 +126,8 @@ struct target_s {
/* Register access functions */ /* Register access functions */
int regs_size; int regs_size;
const char *tdesc; const char *tdesc;
int (*regs_read)(target *t, void *data); void (*regs_read)(target *t, void *data);
int (*regs_write)(target *t, const void *data); void (*regs_write)(target *t, const void *data);
/* Halt/resume functions */ /* Halt/resume functions */
void (*reset)(target *t); void (*reset)(target *t);