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adiv5.c: Format debug output more tense.

This commit is contained in:
Uwe Bonnes 2019-06-24 14:30:05 +02:00
parent 205fce20e5
commit c44cb904b0
1 changed files with 32 additions and 26 deletions
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58
src/target/adiv5.c
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@ -253,12 +253,19 @@ static uint32_t adiv5_mem_read32(ADIv5_AP_t *ap, uint32_t addr)
return ret; return ret;
} }
static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr) static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion, int num_entry)
{ {
(void) num_entry;
addr &= ~3; addr &= ~3;
uint64_t pidr = 0; uint64_t pidr = 0;
uint32_t cidr = 0; uint32_t cidr = 0;
bool res = false; bool res = false;
#if defined(ENABLE_DEBUG)
char indent[recursion];
for(int i = 0; i < recursion; i++) indent[i] = ' ';
indent[recursion] = 0;
#endif
/* Assemble logical Product ID register value. */ /* Assemble logical Product ID register value. */
for (int i = 0; i < 4; i++) { for (int i = 0; i < 4; i++) {
@ -277,14 +284,15 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
} }
if (adiv5_dp_error(ap->dp)) { if (adiv5_dp_error(ap->dp)) {
DEBUG("Fault reading ID registers\n"); DEBUG("%sFault reading ID registers\n", indent);
return false; return false;
} }
/* CIDR preamble sanity check */ /* CIDR preamble sanity check */
if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) { if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) {
DEBUG("0x%"PRIx32": 0x%"PRIx32" <- does not match preamble (0x%X)\n", DEBUG("%s%d 0x%08" PRIx32": 0x%08" PRIx32
addr, cidr, CID_PREAMBLE); " <- does not match preamble (0x%X)\n",
indent + 1, num_entry, addr, cidr, CID_PREAMBLE);
return false; return false;
} }
@ -302,39 +310,37 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
DEBUG("Fault reading ROM table entry\n"); DEBUG("Fault reading ROM table entry\n");
} }
DEBUG("\nROM: Table BASE=0x%"PRIx32" SYSMEM=0x%"PRIx32"\n", DEBUG("ROM: Table BASE=0x%"PRIx32" SYSMEM=0x%"PRIx32"\n",
addr, memtype); addr, memtype);
#endif #endif
for (int i = 0; i < 960; i++) { for (int i = 0; i < 960; i++) {
uint32_t entry = adiv5_mem_read32(ap, addr + i*4); uint32_t entry = adiv5_mem_read32(ap, addr + i*4);
if (adiv5_dp_error(ap->dp)) { if (adiv5_dp_error(ap->dp)) {
DEBUG("Fault reading ROM table entry\n"); DEBUG("%sFault reading ROM table entry\n", indent);
} }
if (entry == 0) if (entry == 0)
break; break;
if (!(entry & ADIV5_ROM_ROMENTRY_PRESENT)) { if (!(entry & ADIV5_ROM_ROMENTRY_PRESENT)) {
DEBUG("%d Entry 0x%"PRIx32" -> Not present\n", i, entry); DEBUG("%s%d Entry 0x%"PRIx32" -> Not present\n", indent, i, entry);
continue; continue;
} }
DEBUG("%d Entry 0x%"PRIx32" -> 0x%"PRIx32"\n",
i, entry, addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET));
/* Probe recursively */ /* Probe recursively */
res |= adiv5_component_probe(ap, res |= adiv5_component_probe(
addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET)); ap, addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET),
recursion + 1, i);
} }
DEBUG("ROM: Table END\n\n"); DEBUG("%sROM: Table END\n", indent);
} else { } else {
/* Check if the component was designed by ARM, we currently do not support, /* Check if the component was designed by ARM, we currently do not support,
* any components by other designers. * any components by other designers.
*/ */
if ((pidr & ~(PIDR_REV_MASK | PIDR_PN_MASK)) != PIDR_ARM_BITS) { if ((pidr & ~(PIDR_REV_MASK | PIDR_PN_MASK)) != PIDR_ARM_BITS) {
DEBUG("0x%"PRIx32": 0x%"PRIx64" <- does not match ARM JEP-106\n", DEBUG("%s0x%"PRIx32": 0x%"PRIx64" <- does not match ARM JEP-106\n",
addr, pidr); indent, addr, pidr);
return false; return false;
} }
@ -346,38 +352,38 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
int i; int i;
for (i = 0; pidr_pn_bits[i].arch != aa_end; i++) { for (i = 0; pidr_pn_bits[i].arch != aa_end; i++) {
if (pidr_pn_bits[i].part_number == part_number) { if (pidr_pn_bits[i].part_number == part_number) {
DEBUG("0x%"PRIx32": %s - %s %s (PIDR = 0x%"PRIx64")\n", addr, DEBUG("%s%d 0x%"PRIx32": %s - %s %s (PIDR = 0x%"PRIx64")",
cidc_debug_strings[cid_class], indent + 1, num_entry, addr, cidc_debug_strings[cid_class],
pidr_pn_bits[i].type, pidr_pn_bits[i].type, pidr_pn_bits[i].full, pidr);
pidr_pn_bits[i].full, pidr);
/* Perform sanity check, if we know what to expect as component ID /* Perform sanity check, if we know what to expect as component ID
* class. * class.
*/ */
if ((pidr_pn_bits[i].cidc != cidc_unknown) && if ((pidr_pn_bits[i].cidc != cidc_unknown) &&
(cid_class != pidr_pn_bits[i].cidc)) { (cid_class != pidr_pn_bits[i].cidc)) {
DEBUG("WARNING: \"%s\" !match expected \"%s\"\n", DEBUG("%sWARNING: \"%s\" !match expected \"%s\"\n", indent + 1,
cidc_debug_strings[cid_class], cidc_debug_strings[cid_class],
cidc_debug_strings[pidr_pn_bits[i].cidc]); cidc_debug_strings[pidr_pn_bits[i].cidc]);
} }
res = true; res = true;
switch (pidr_pn_bits[i].arch) { switch (pidr_pn_bits[i].arch) {
case aa_cortexm: case aa_cortexm:
DEBUG("-> cortexm_probe\n"); DEBUG("%s-> cortexm_probe\n", indent + 1);
cortexm_probe(ap, false); cortexm_probe(ap, false);
break; break;
case aa_cortexa: case aa_cortexa:
DEBUG("-> cortexa_probe\n"); DEBUG("%s-> cortexa_probe\n", indent + 1);
cortexa_probe(ap, addr); cortexa_probe(ap, addr);
break; break;
default: default:
DEBUG("\n");
break; break;
} }
break; break;
} }
} }
if (pidr_pn_bits[i].arch == aa_end) { if (pidr_pn_bits[i].arch == aa_end) {
DEBUG("0x%"PRIx32": %s - Unknown (PIDR = 0x%"PRIx64")\n", addr, DEBUG("%s0x%"PRIx32": %s - Unknown (PIDR = 0x%"PRIx64")\n",
cidc_debug_strings[cid_class], pidr); indent, addr, cidc_debug_strings[cid_class], pidr);
} }
} }
return res; return res;
@ -418,7 +424,7 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
ap->csw &= ~ADIV5_AP_CSW_TRINPROG; ap->csw &= ~ADIV5_AP_CSW_TRINPROG;
} }
DEBUG(" AP %3d: IDR=%08"PRIx32" CFG=%08"PRIx32" BASE=%08"PRIx32" CSW=%08"PRIx32"\n", DEBUG("AP %3d: IDR=%08"PRIx32" CFG=%08"PRIx32" BASE=%08"PRIx32" CSW=%08"PRIx32"\n",
apsel, ap->idr, ap->cfg, ap->base, ap->csw); apsel, ap->idr, ap->cfg, ap->base, ap->csw);
return ap; return ap;
} }
@ -507,7 +513,7 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
*/ */
/* The rest should only be added after checking ROM table */ /* The rest should only be added after checking ROM table */
probed |= adiv5_component_probe(ap, ap->base); probed |= adiv5_component_probe(ap, ap->base, 0, 0);
if (!probed && (dp->idcode & 0xfff) == 0x477) { if (!probed && (dp->idcode & 0xfff) == 0x477) {
DEBUG("-> cortexm_probe forced\n"); DEBUG("-> cortexm_probe forced\n");
cortexm_probe(ap, true); cortexm_probe(ap, true);