adiv5.c: Format debug output more tense.
This commit is contained in:
Uwe Bonnes
parent
205fce20e5
commit
c44cb904b0
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@ -253,12 +253,19 @@ static uint32_t adiv5_mem_read32(ADIv5_AP_t *ap, uint32_t addr)
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return ret;
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}
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static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
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static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion, int num_entry)
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{
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(void) num_entry;
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addr &= ~3;
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uint64_t pidr = 0;
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uint32_t cidr = 0;
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bool res = false;
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#if defined(ENABLE_DEBUG)
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char indent[recursion];
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for(int i = 0; i < recursion; i++) indent[i] = ' ';
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indent[recursion] = 0;
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#endif
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/* Assemble logical Product ID register value. */
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for (int i = 0; i < 4; i++) {
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@ -277,14 +284,15 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
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}
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if (adiv5_dp_error(ap->dp)) {
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DEBUG("Fault reading ID registers\n");
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DEBUG("%sFault reading ID registers\n", indent);
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return false;
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}
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/* CIDR preamble sanity check */
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if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) {
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DEBUG("0x%"PRIx32": 0x%"PRIx32" <- does not match preamble (0x%X)\n",
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addr, cidr, CID_PREAMBLE);
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DEBUG("%s%d 0x%08" PRIx32": 0x%08" PRIx32
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" <- does not match preamble (0x%X)\n",
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indent + 1, num_entry, addr, cidr, CID_PREAMBLE);
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return false;
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}
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@ -302,39 +310,37 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
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DEBUG("Fault reading ROM table entry\n");
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}
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DEBUG("\nROM: Table BASE=0x%"PRIx32" SYSMEM=0x%"PRIx32"\n",
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DEBUG("ROM: Table BASE=0x%"PRIx32" SYSMEM=0x%"PRIx32"\n",
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addr, memtype);
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#endif
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for (int i = 0; i < 960; i++) {
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uint32_t entry = adiv5_mem_read32(ap, addr + i*4);
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if (adiv5_dp_error(ap->dp)) {
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DEBUG("Fault reading ROM table entry\n");
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DEBUG("%sFault reading ROM table entry\n", indent);
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}
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if (entry == 0)
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break;
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if (!(entry & ADIV5_ROM_ROMENTRY_PRESENT)) {
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DEBUG("%d Entry 0x%"PRIx32" -> Not present\n", i, entry);
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DEBUG("%s%d Entry 0x%"PRIx32" -> Not present\n", indent, i, entry);
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continue;
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}
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DEBUG("%d Entry 0x%"PRIx32" -> 0x%"PRIx32"\n",
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i, entry, addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET));
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/* Probe recursively */
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res |= adiv5_component_probe(ap,
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addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET));
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res |= adiv5_component_probe(
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ap, addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET),
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recursion + 1, i);
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}
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DEBUG("ROM: Table END\n\n");
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DEBUG("%sROM: Table END\n", indent);
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} else {
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/* Check if the component was designed by ARM, we currently do not support,
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* any components by other designers.
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*/
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if ((pidr & ~(PIDR_REV_MASK | PIDR_PN_MASK)) != PIDR_ARM_BITS) {
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DEBUG("0x%"PRIx32": 0x%"PRIx64" <- does not match ARM JEP-106\n",
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addr, pidr);
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DEBUG("%s0x%"PRIx32": 0x%"PRIx64" <- does not match ARM JEP-106\n",
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indent, addr, pidr);
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return false;
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}
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@ -346,38 +352,38 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
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int i;
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for (i = 0; pidr_pn_bits[i].arch != aa_end; i++) {
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if (pidr_pn_bits[i].part_number == part_number) {
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DEBUG("0x%"PRIx32": %s - %s %s (PIDR = 0x%"PRIx64")\n", addr,
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cidc_debug_strings[cid_class],
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pidr_pn_bits[i].type,
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pidr_pn_bits[i].full, pidr);
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DEBUG("%s%d 0x%"PRIx32": %s - %s %s (PIDR = 0x%"PRIx64")",
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indent + 1, num_entry, addr, cidc_debug_strings[cid_class],
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pidr_pn_bits[i].type, pidr_pn_bits[i].full, pidr);
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/* Perform sanity check, if we know what to expect as component ID
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* class.
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*/
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if ((pidr_pn_bits[i].cidc != cidc_unknown) &&
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(cid_class != pidr_pn_bits[i].cidc)) {
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DEBUG("WARNING: \"%s\" !match expected \"%s\"\n",
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DEBUG("%sWARNING: \"%s\" !match expected \"%s\"\n", indent + 1,
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cidc_debug_strings[cid_class],
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cidc_debug_strings[pidr_pn_bits[i].cidc]);
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}
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res = true;
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switch (pidr_pn_bits[i].arch) {
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case aa_cortexm:
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DEBUG("-> cortexm_probe\n");
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DEBUG("%s-> cortexm_probe\n", indent + 1);
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cortexm_probe(ap, false);
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break;
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case aa_cortexa:
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DEBUG("-> cortexa_probe\n");
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DEBUG("%s-> cortexa_probe\n", indent + 1);
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cortexa_probe(ap, addr);
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break;
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default:
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DEBUG("\n");
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break;
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}
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break;
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}
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}
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if (pidr_pn_bits[i].arch == aa_end) {
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DEBUG("0x%"PRIx32": %s - Unknown (PIDR = 0x%"PRIx64")\n", addr,
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cidc_debug_strings[cid_class], pidr);
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DEBUG("%s0x%"PRIx32": %s - Unknown (PIDR = 0x%"PRIx64")\n",
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indent, addr, cidc_debug_strings[cid_class], pidr);
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}
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}
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return res;
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@ -418,7 +424,7 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
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ap->csw &= ~ADIV5_AP_CSW_TRINPROG;
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}
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DEBUG(" AP %3d: IDR=%08"PRIx32" CFG=%08"PRIx32" BASE=%08"PRIx32" CSW=%08"PRIx32"\n",
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DEBUG("AP %3d: IDR=%08"PRIx32" CFG=%08"PRIx32" BASE=%08"PRIx32" CSW=%08"PRIx32"\n",
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apsel, ap->idr, ap->cfg, ap->base, ap->csw);
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return ap;
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}
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@ -507,7 +513,7 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
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*/
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/* The rest should only be added after checking ROM table */
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probed |= adiv5_component_probe(ap, ap->base);
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probed |= adiv5_component_probe(ap, ap->base, 0, 0);
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if (!probed && (dp->idcode & 0xfff) == 0x477) {
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DEBUG("-> cortexm_probe forced\n");
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cortexm_probe(ap, true);
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