stm32f4.c: Rework flash structure recognition.
Dual bank devices do not have sectors (8)12..15 ! Dual banks devices need to MER1 set for mass erase. F72x has different FLASHSIZE_BASE
This commit is contained in:
Uwe Bonnes
parent
ad71db05b9
commit
c4d3712b39
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@ -40,21 +40,20 @@ static bool stm32f4_cmd_option(target *t, int argc, char *argv[]);
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static bool stm32f4_cmd_psize(target *t, int argc, char *argv[]);
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const struct command_s stm32f4_cmd_list[] = {
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{"erase_mass", (cmd_handler)stm32f4_cmd_erase_mass, "Erase entire flash memory"},
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{"erase_mass", (cmd_handler)stm32f4_cmd_erase_mass,
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"Erase entire flash memory"},
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{"option", (cmd_handler)stm32f4_cmd_option, "Manipulate option bytes"},
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{"psize", (cmd_handler)stm32f4_cmd_psize, "Configure flash write parallelism: (x8|x32)"},
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{"psize", (cmd_handler)stm32f4_cmd_psize,
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"Configure flash write parallelism: (x8|x32(default))"},
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{NULL, NULL, NULL}
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};
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static int stm32f4_flash_erase(struct target_flash *f, target_addr addr, size_t len);
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static int stm32f4_flash_erase(struct target_flash *f, target_addr addr,
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size_t len);
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static int stm32f4_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len);
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static const char stm32f4_driver_str[] = "STM32F4xx";
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static const char stm32f7_driver_str[] = "STM32F7xx";
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static const char stm32f2_driver_str[] = "STM32F2xx";
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/* Flash Program ad Erase Controller Register Map */
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#define FPEC_BASE 0x40023C00
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#define FLASH_ACR (FPEC_BASE+0x00)
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@ -71,6 +70,7 @@ static const char stm32f2_driver_str[] = "STM32F2xx";
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#define FLASH_CR_PSIZE16 (1 << 8)
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#define FLASH_CR_PSIZE32 (2 << 8)
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#define FLASH_CR_PSIZE64 (3 << 8)
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#define FLASH_CR_MER1 (1 << 15)
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#define FLASH_CR_STRT (1 << 16)
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#define FLASH_CR_EOPIE (1 << 24)
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#define FLASH_CR_ERRIE (1 << 25)
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@ -81,6 +81,8 @@ static const char stm32f2_driver_str[] = "STM32F2xx";
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#define FLASH_OPTCR_OPTLOCK (1 << 0)
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#define FLASH_OPTCR_OPTSTRT (1 << 1)
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#define FLASH_OPTCR_nDBANK (1 << 29)
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#define FLASH_OPTCR_DB1M (1 << 30)
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#define KEY1 0x45670123
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#define KEY2 0xCDEF89AB
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@ -91,6 +93,9 @@ static const char stm32f2_driver_str[] = "STM32F2xx";
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#define SR_ERROR_MASK 0xF2
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#define SR_EOP 0x01
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#define F4_FLASHSIZE 0x1FFF7A22
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#define F7_FLASHSIZE 0x1FF0F442
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#define F72X_FLASHSIZE 0x1FF07A22
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#define DBGMCU_IDCODE 0xE0042000
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#define ARM_CPUID 0xE000ED00
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@ -125,6 +130,7 @@ struct stm32f4_flash {
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struct target_flash f;
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uint8_t base_sector;
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uint8_t psize;
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uint8_t bank_split;
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};
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enum ID_STM32F47 {
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@ -146,7 +152,7 @@ enum ID_STM32F47 {
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static void stm32f4_add_flash(target *t,
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uint32_t addr, size_t length, size_t blocksize,
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uint8_t base_sector)
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unsigned int base_sector, int split)
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{
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struct stm32f4_flash *sf = calloc(1, sizeof(*sf));
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struct target_flash *f = &sf->f;
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@ -159,104 +165,155 @@ static void stm32f4_add_flash(target *t,
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f->erased = 0xff;
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sf->base_sector = base_sector;
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sf->psize = 32;
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sf->bank_split = split;
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target_add_flash(t, f);
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}
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bool stm32f4_probe(target *t)
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{
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bool f2 = false;
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uint32_t idcode;
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const char* designator = NULL;
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bool dual_bank = false;
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bool has_ccmram = false;
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bool is_f7 = false;
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bool large_sectors = false;
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uint32_t flashsize_base = F4_FLASHSIZE;
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idcode = target_mem_read32(t, DBGMCU_IDCODE);
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idcode &= 0xFFF;
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if (idcode == ID_STM32F20X)
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{
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if (idcode == ID_STM32F20X) {
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/* F405 revision A have a wrong IDCODE, use ARM_CPUID to make the
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* distinction with F205. Revision is also wrong (0x2000 instead
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* of 0x1000). See F40x/F41x errata. */
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uint32_t cpuid = target_mem_read32(t, ARM_CPUID);
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if ((cpuid & 0xFFF0) == 0xC240)
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idcode = ID_STM32F40X;
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else
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f2 = true;
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}
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switch(idcode) {
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case ID_STM32F40X:
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designator = "STM32F40x";
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has_ccmram = true;
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break;
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case ID_STM32F42X: /* 427/437 */
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designator = "STM32F42x";
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has_ccmram = true;
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dual_bank = true;
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break;
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case ID_STM32F46X: /* 469/479 */
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/* Second bank for 2M parts. */
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stm32f4_add_flash(t, 0x8100000, 0x10000, 0x4000, 12);
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stm32f4_add_flash(t, 0x8110000, 0x10000, 0x10000, 16);
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stm32f4_add_flash(t, 0x8120000, 0xE0000, 0x20000, 17);
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/* Fall through for stuff common to F40x/F41x */
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designator = "STM32F47x";
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has_ccmram = true;
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dual_bank = true;
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break;
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case ID_STM32F20X: /* F205 */
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case ID_STM32F40X: /* F405 */
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if (!f2)
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target_add_ram(t, 0x10000000, 0x10000);
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/* Fall through for devices w/o CCMRAM */
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designator = "STM32F2";
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break;
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case ID_STM32F446: /* F446 */
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designator = "STM32F446";
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break;
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case ID_STM32F401C: /* F401 B/C RM0368 Rev.3 */
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designator = "STM32F401C";
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break;
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case ID_STM32F411: /* F411 RM0383 Rev.4 */
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designator = "STM32F411";
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break;
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case ID_STM32F412: /* F412 RM0402 Rev.4, 256 kB Ram */
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designator = "STM32F412";
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break;
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case ID_STM32F401E: /* F401 D/E RM0368 Rev.3 */
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t->driver = f2 ? stm32f2_driver_str : stm32f4_driver_str;
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target_add_ram(t, 0x20000000, 0x40000);
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stm32f4_add_flash(t, 0x8000000, 0x10000, 0x4000, 0);
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stm32f4_add_flash(t, 0x8010000, 0x10000, 0x10000, 4);
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stm32f4_add_flash(t, 0x8020000, 0xE0000, 0x20000, 5);
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target_add_commands(t, stm32f4_cmd_list, f2 ? "STM32F2" :
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"STM32F4");
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designator = "STM32F401E";
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break;
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case ID_STM32F413: /* F413 RM0430 Rev.2, 320 kB Ram, 1.5 MB flash. */
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t->driver = stm32f4_driver_str;
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target_add_ram(t, 0x20000000, 0x50000);
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stm32f4_add_flash(t, 0x8000000, 0x10000, 0x4000, 0);
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stm32f4_add_flash(t, 0x8010000, 0x10000, 0x10000, 4);
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stm32f4_add_flash(t, 0x8020000, 0x160000, 0x20000, 5);
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target_add_commands(t, stm32f4_cmd_list, "STM32F413");
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designator = "STM32F413";
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break;
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case ID_STM32F74X: /* F74x RM0385 Rev.4 */
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t->driver = stm32f7_driver_str;
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target_add_ram(t, 0x00000000, 0x4000);
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target_add_ram(t, 0x20000000, 0x50000);
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/* AXIM Flash access */
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stm32f4_add_flash(t, 0x8000000, 0x20000, 0x8000, 0);
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stm32f4_add_flash(t, 0x8020000, 0x20000, 0x20000, 4);
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stm32f4_add_flash(t, 0x8040000, 0xC0000, 0x40000, 5);
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/* Flash aliased as ITCM */
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stm32f4_add_flash(t, 0x0200000, 0x20000, 0x8000, 0);
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stm32f4_add_flash(t, 0x0220000, 0x20000, 0x20000, 4);
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stm32f4_add_flash(t, 0x0240000, 0xC0000, 0x40000, 5);
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target_add_commands(t, stm32f4_cmd_list, "STM32F74x");
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designator = "STM32F74x";
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is_f7 = true;
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large_sectors = true;
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flashsize_base = F7_FLASHSIZE;
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break;
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case ID_STM32F76X: /* F76x F77x RM0410 */
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t->driver = stm32f7_driver_str;
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target_add_ram(t, 0x00000000, 0x4000);
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target_add_ram(t, 0x20000000, 0x80000);
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/* AXIM Flash access */
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stm32f4_add_flash(t, 0x8000000, 0x020000, 0x8000, 0);
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stm32f4_add_flash(t, 0x8020000, 0x020000, 0x20000, 4);
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stm32f4_add_flash(t, 0x8040000, 0x1C0000, 0x40000, 5);
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/* Flash aliased as ITCM */
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stm32f4_add_flash(t, 0x200000, 0x020000, 0x8000, 0);
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stm32f4_add_flash(t, 0x220000, 0x020000, 0x20000, 4);
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stm32f4_add_flash(t, 0x240000, 0x1C0000, 0x40000, 5);
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target_add_commands(t, stm32f4_cmd_list, "STM32F76x");
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designator = "STM32F76x";
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is_f7 = true;
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dual_bank = true;
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flashsize_base = F7_FLASHSIZE;
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break;
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case ID_STM32F72X: /* F72x F73x RM0431 */
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t->driver = stm32f7_driver_str;
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target_add_ram(t, 0x00000000, 0x2000);
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target_add_ram(t, 0x20000000, 0x40000);
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stm32f4_add_flash(t, 0x8000000, 0x010000, 0x4000, 0);
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stm32f4_add_flash(t, 0x8010000, 0x010000, 0x10000, 4);
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stm32f4_add_flash(t, 0x8020000, 0x060000, 0x20000, 3);
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target_add_commands(t, stm32f4_cmd_list, "STM32F72x");
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designator = "STM32F72x";
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is_f7 = true;
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flashsize_base = F72X_FLASHSIZE;
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break;
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default:
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return false;
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}
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target_mem_write32(t, DBGMCU_CR, DBG_STANDBY| DBG_STOP | DBG_SLEEP);
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t->driver = designator;
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target_add_commands(t, stm32f4_cmd_list, designator);
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t->idcode = idcode;
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bool use_dual_bank = false;
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uint32_t flashsize = target_mem_read32(t, flashsize_base) & 0xffff;
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if (is_f7) {
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target_add_ram(t, 0x00000000, 0x4000); /* 16 k ITCM Ram */
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target_add_ram(t, 0x20000000, 0x10000); /* 64 k DTCM Ram */
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if (dual_bank) {
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uint32_t optcr;
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optcr = target_mem_read32(t, FLASH_OPTCR);
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use_dual_bank = !(optcr & FLASH_OPTCR_nDBANK);
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}
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} else {
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if (has_ccmram)
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target_add_ram(t, 0x10000000, 0x10000); /* 64 k CCM Ram*/
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target_add_ram(t, 0x20000000, 0x10000); /* 64 k RAM */
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if (dual_bank) {
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use_dual_bank = true;
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if (flashsize < 0x800) {
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/* Check Dual-bank on 1 Mbyte Flash memory devices*/
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uint32_t optcr;
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optcr = target_mem_read32(t, FLASH_OPTCR);
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use_dual_bank = !(optcr & FLASH_OPTCR_DB1M);
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}
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}
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}
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int split = 0;
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uint32_t banksize;
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if (use_dual_bank) {
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banksize = flashsize << 9; /* flas split on two sectors. */
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split = (flashsize == 0x400) ? 8 : 12;
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}
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else
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banksize = flashsize << 10;
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if (large_sectors) {
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uint32_t remains = banksize - 0x40000;
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/* 256 k in small sectors.*/
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stm32f4_add_flash(t, ITCM_BASE, 0x20000, 0x8000, 0, split);
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stm32f4_add_flash(t, 0x0220000, 0x20000, 0x20000, 4, split);
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stm32f4_add_flash(t, 0x0240000, remains, 0x40000, 5, split);
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stm32f4_add_flash(t, AXIM_BASE, 0x20000, 0x8000, 0, split);
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stm32f4_add_flash(t, 0x8020000, 0x20000, 0x20000, 4, split);
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stm32f4_add_flash(t, 0x8040000, remains, 0x40000, 5, split);
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} else {
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uint32_t remains = banksize - 0x20000; /* 128 k in small sectors.*/
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if (is_f7) {
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stm32f4_add_flash(t, ITCM_BASE, 0x10000, 0x4000, 0, split);
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stm32f4_add_flash(t, 0x0210000, 0x10000, 0x10000, 4, split);
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stm32f4_add_flash(t, 0x0220000, remains, 0x20000, 5, split);
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}
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stm32f4_add_flash(t, 0x8000000, 0x10000, 0x4000, 0, split);
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stm32f4_add_flash(t, 0x8010000, 0x10000, 0x10000, 4, split);
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stm32f4_add_flash(t, 0x8020000, remains, 0x20000, 5, split);
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if (use_dual_bank) {
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if (is_f7) {
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uint32_t bk1 = ITCM_BASE + banksize;
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stm32f4_add_flash(t, bk1 , 0x10000, 0x4000, 0, split);
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stm32f4_add_flash(t, bk1 + 0x10000, 0x10000, 0x10000, 4, split);
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stm32f4_add_flash(t, bk1 + 0x20000, remains, 0x20000, 5, split);
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}
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uint32_t bk2 = 0x8000000 + banksize;
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stm32f4_add_flash(t, bk2 , 0x10000, 0x4000, 16, split);
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stm32f4_add_flash(t, bk2 + 0x10000, 0x10000, 0x10000, 20, split);
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stm32f4_add_flash(t, bk2 + 0x20000, remains, 0x20000, 21, split);
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}
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}
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return true;
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}
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@ -269,14 +326,14 @@ static void stm32f4_flash_unlock(target *t)
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}
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}
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static int stm32f4_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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static int stm32f4_flash_erase(struct target_flash *f, target_addr addr,
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size_t len)
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{
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target *t = f->t;
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uint16_t sr;
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struct stm32f4_flash *sf = (struct stm32f4_flash *)f;
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uint32_t sr;
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/* No address translation is needed here, as we erase by sector number */
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uint8_t sector = ((struct stm32f4_flash *)f)->base_sector +
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(addr - f->start)/f->blocksize;
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uint8_t sector = sf->base_sector + (addr - f->start)/f->blocksize;
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stm32f4_flash_unlock(t);
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while(len) {
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@ -289,18 +346,22 @@ static int stm32f4_flash_erase(struct target_flash *f, target_addr addr, size_t
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/* Read FLASH_SR to poll for BSY bit */
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while(target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(t))
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if(target_check_error(t)) {
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DEBUG("stm32f4 flash erase: comm error\n");
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return -1;
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}
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len -= f->blocksize;
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sector++;
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if ((sf->bank_split) && (sector == sf->bank_split))
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sector = 16;
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}
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/* Check for error */
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sr = target_mem_read32(t, FLASH_SR);
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if(sr & SR_ERROR_MASK)
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if(sr & SR_ERROR_MASK) {
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DEBUG("stm32f4 flash erase: sr error: 0x%" PRIu32 "\n", sr);
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return -1;
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}
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return 0;
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}
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@ -328,13 +389,18 @@ static bool stm32f4_cmd_erase_mass(target *t)
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{
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const char spinner[] = "|/-\\";
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int spinindex = 0;
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struct target_flash *f = t->flash;
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struct stm32f4_flash *sf = (struct stm32f4_flash *)f;
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tc_printf(t, "Erasing flash... This may take a few seconds. ");
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stm32f4_flash_unlock(t);
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/* Flash mass erase start instruction */
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target_mem_write32(t, FLASH_CR, FLASH_CR_MER);
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target_mem_write32(t, FLASH_CR, FLASH_CR_STRT | FLASH_CR_MER);
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uint32_t cr = FLASH_CR_MER;
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if (sf->bank_split)
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cr |= FLASH_CR_MER1;
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target_mem_write32(t, FLASH_CR, cr);
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target_mem_write32(t, FLASH_CR, cr | FLASH_CR_STRT);
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/* Read FLASH_SR to poll for BSY bit */
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while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) {
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@ -347,7 +413,7 @@ static bool stm32f4_cmd_erase_mass(target *t)
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tc_printf(t, "\n");
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/* Check for error */
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uint16_t sr = target_mem_read32(t, FLASH_SR);
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uint32_t sr = target_mem_read32(t, FLASH_SR);
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if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP))
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return false;
|
||||
|
||||
|
|
|
|||
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Reference in New Issue