Cleaned out some magic numbers in cortexm3.c
This commit is contained in:
Gareth McMullin
parent
c43e392f8c
commit
c648d7c9e2
src
118
src/cortexm3.c
118
src/cortexm3.c
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@ -40,17 +40,72 @@
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static char cm3_driver_str[] = "ARM Cortex-M3";
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/* Private peripheral bus base address */
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#define CM3_PPB_BASE 0xE0000000
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#define CM3_SCS_BASE (CM3_PPB_BASE + 0xE000)
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#define CM3_DHCSR (CM3_SCS_BASE + 0xDF0)
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#define CM3_DCRSR (CM3_SCS_BASE + 0xDF4)
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#define CM3_DCRDR (CM3_SCS_BASE + 0xDF8)
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#define CM3_DEMCR (CM3_SCS_BASE + 0xDFC)
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/* Debug Halting Control and Status Register (DHCSR) */
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/* This key must be written to bits 31:16 for write to take effect */
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#define CM3_DHCSR_DBGKEY 0xA05F0000
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/* Bits 31:26 - Reserved */
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#define CM3_DHCSR_S_RESET_ST (1 << 25)
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#define CM3_DHCSR_S_RETIRE_ST (1 << 24)
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/* Bits 23:20 - Reserved */
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#define CM3_DHCSR_S_LOCKUP (1 << 19)
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#define CM3_DHCSR_S_SLEEP (1 << 18)
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#define CM3_DHCSR_S_HALT (1 << 17)
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#define CM3_DHCSR_S_REGRDY (1 << 16)
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/* Bits 15:6 - Reserved */
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#define CM3_DHCSR_C_SNAPSTALL (1 << 5)
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/* Bit 4 - Reserved */
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#define CM3_DHCSR_C_MASKINTS (1 << 3)
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#define CM3_DHCSR_C_STEP (1 << 2)
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#define CM3_DHCSR_C_HALT (1 << 1)
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#define CM3_DHCSR_C_DEBUGEN (1 << 0)
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/* Debug Core Register Selector Register (DCRSR) */
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#define CM3_DCRSR_REGSEL_MASK 0x0000001F
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#define CM3_DCRSR_REGSEL_XPSR 0x00000010
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#define CM3_DCRSR_REGSEL_MSP 0x00000011
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#define CM3_DCRSR_REGSEL_PSP 0x00000012
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/* Debug Exception and Monitor Control Register (DEMCR) */
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/* Bits 31:25 - Reserved */
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#define CM3_DEMCR_TRCENA (1 << 24)
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/* Bits 23:20 - Reserved */
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#define CM3_DEMCR_MON_REQ (1 << 19)
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#define CM3_DEMCR_MON_STEP (1 << 18)
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#define CM3_DEMCR_VC_MON_PEND (1 << 17)
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#define CM3_DEMCR_VC_MON_EN (1 << 16)
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/* Bits 15:11 - Reserved */
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#define CM3_DEMCR_VC_HARDERR (1 << 10)
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#define CM3_DEMCR_VC_INTERR (1 << 9)
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#define CM3_DEMCR_VC_BUSERR (1 << 8)
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#define CM3_DEMCR_VC_STATERR (1 << 7)
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#define CM3_DEMCR_VC_CHKERR (1 << 6)
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#define CM3_DEMCR_VC_NOCPERR (1 << 5)
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#define CM3_DEMCR_VC_MMERR (1 << 4)
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/* Bits 3:1 - Reserved */
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#define CM3_DEMCR_VC_CORERESET (1 << 0)
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static void cm3_attach(struct target_s *target);
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static void cm3_detach(struct target_s *target);
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static int ap_regs_read(struct target_s *target, void *data);
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static int ap_regs_write(struct target_s *target, const void *data);
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static int ap_pc_write(struct target_s *target, const uint32_t val);
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static int cm3_regs_read(struct target_s *target, void *data);
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static int cm3_regs_write(struct target_s *target, const void *data);
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static int cm3_pc_write(struct target_s *target, const uint32_t val);
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static void cm3_reset(struct target_s *target);
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static void ap_halt_resume(struct target_s *target, uint8_t step);
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static int ap_halt_wait(struct target_s *target);
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static void ap_halt_request(struct target_s *target);
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static void cm3_halt_resume(struct target_s *target, uint8_t step);
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static int cm3_halt_wait(struct target_s *target);
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static void cm3_halt_request(struct target_s *target);
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static int cm3_fault_unwind(struct target_s *target);
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static int cm3_set_hw_bp(struct target_s *target, uint32_t addr);
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@ -80,15 +135,14 @@ cm3_probe(struct target_s *target)
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target->detach = cm3_detach;
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/* Should probe here to make sure it's Cortex-M3 */
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target->regs_read = ap_regs_read;
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target->regs_write = ap_regs_write;
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// target->pc_read = ap_pc_read;
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target->pc_write = ap_pc_write;
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target->regs_read = cm3_regs_read;
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target->regs_write = cm3_regs_write;
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target->pc_write = cm3_pc_write;
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target->reset = cm3_reset;
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target->halt_request = ap_halt_request;
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target->halt_wait = ap_halt_wait;
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target->halt_resume = ap_halt_resume;
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target->halt_request = cm3_halt_request;
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target->halt_wait = cm3_halt_wait;
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target->halt_resume = cm3_halt_resume;
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target->fault_unwind = cm3_fault_unwind;
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target->regs_size = 16<<2;
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@ -109,8 +163,9 @@ cm3_attach(struct target_s *target)
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while(!target_halt_wait(target));
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/* Request halt on reset */
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/* TRCENA | VC_CORERESET */
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adiv5_ap_mem_write(t->ap, 0xE000EDFC, 0x01000401);
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adiv5_ap_mem_write(t->ap, CM3_DEMCR,
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CM3_DEMCR_TRCENA | CM3_DEMCR_VC_HARDERR |
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CM3_DEMCR_VC_CORERESET);
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/* Reset DFSR flags */
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adiv5_ap_mem_write(t->ap, 0xE000ED30UL, 0x1F);
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@ -153,16 +208,17 @@ cm3_detach(struct target_s *target)
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adiv5_ap_mem_write(t->ap, 0xE0001028 + i*0x10, 0);
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/* Disable debug */
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adiv5_ap_mem_write(t->ap, 0xE000EDF0UL, 0xA05F0000UL);
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adiv5_ap_mem_write(t->ap, CM3_DHCSR, CM3_DHCSR_DBGKEY);
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}
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static int
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ap_regs_read(struct target_s *target, void *data)
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cm3_regs_read(struct target_s *target, void *data)
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{
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struct target_ap_s *t = (void *)target;
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uint32_t *regs = data;
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int i;
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/* FIXME: Describe what's really going on here */
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adiv5_ap_write(t->ap, 0x00, 0xA2000052);
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adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, 0xE000EDF0);
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adiv5_ap_write(t->ap, 0x14, 0); /* Required to switch banks */
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@ -176,12 +232,13 @@ ap_regs_read(struct target_s *target, void *data)
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}
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static int
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ap_regs_write(struct target_s *target, const void *data)
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cm3_regs_write(struct target_s *target, const void *data)
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{
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struct target_ap_s *t = (void *)target;
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const uint32_t *regs = data;
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int i;
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/* FIXME: Describe what's really going on here */
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adiv5_ap_write(t->ap, 0x00, 0xA2000052);
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adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, 0xE000EDF0);
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adiv5_ap_write(t->ap, 0x18, *regs++); /* Required to switch banks */
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@ -195,7 +252,7 @@ ap_regs_write(struct target_s *target, const void *data)
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}
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static int
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ap_pc_write(struct target_s *target, const uint32_t val)
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cm3_pc_write(struct target_s *target, const uint32_t val)
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{
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struct target_ap_s *t = (void *)target;
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@ -232,35 +289,38 @@ cm3_reset(struct target_s *target)
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}
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static void
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ap_halt_request(struct target_s *target)
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cm3_halt_request(struct target_s *target)
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{
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struct target_ap_s *t = (void *)target;
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adiv5_ap_mem_write(t->ap, 0xE000EDF0UL, 0xA05F0003UL);
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adiv5_ap_mem_write(t->ap, CM3_DHCSR,
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CM3_DHCSR_DBGKEY | CM3_DHCSR_C_HALT | CM3_DHCSR_C_DEBUGEN);
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}
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static int
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ap_halt_wait(struct target_s *target)
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cm3_halt_wait(struct target_s *target)
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{
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struct target_ap_s *t = (void *)target;
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return adiv5_ap_mem_read(t->ap, 0xE000EDF0UL) & 0x20000;
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return adiv5_ap_mem_read(t->ap, CM3_DHCSR) & CM3_DHCSR_S_HALT;
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}
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static void
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ap_halt_resume(struct target_s *target, uint8_t step)
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cm3_halt_resume(struct target_s *target, uint8_t step)
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{
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struct target_ap_s *t = (void *)target;
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static uint8_t old_step = 0;
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uint32_t dhcsr = CM3_DHCSR_DBGKEY | CM3_DHCSR_C_DEBUGEN;
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if(step) dhcsr |= CM3_DHCSR_C_STEP | CM3_DHCSR_C_MASKINTS;
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/* Disable interrupts while single stepping... */
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if(step != old_step) {
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adiv5_ap_mem_write(t->ap, 0xE000EDF0UL,
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step?0xA05F000FUL:0xA05F0003UL);
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adiv5_ap_mem_write(t->ap, CM3_DHCSR, dhcsr | CM3_DHCSR_C_HALT);
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old_step = step;
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}
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adiv5_ap_mem_write(t->ap, 0xE000EDF0UL, step?0xA05F000DUL:0xA05F0001UL);
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adiv5_ap_mem_write(t->ap, CM3_DHCSR, dhcsr);
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}
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static int cm3_fault_unwind(struct target_s *target)
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@ -274,7 +334,7 @@ static int cm3_fault_unwind(struct target_s *target)
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uint32_t regs[16];
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uint32_t stack[8];
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/* Read registers for post-exception stack pointer */
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ap_regs_read(target, regs);
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target_regs_read(target, regs);
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/* Read stack for pre-exception registers */
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target_mem_read_words(target, stack, regs[13], sizeof(stack));
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regs[13] += sizeof(stack); /* Adjust SP for pop */
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@ -288,7 +348,7 @@ static int cm3_fault_unwind(struct target_s *target)
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/* FIXME: stack[7] contains xPSR when this is supported */
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/* Write pre-exception registers back to core */
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ap_regs_write(target, regs);
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target_regs_write(target, regs);
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return 1;
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}
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