Fixed run command on SAM D20 old revision B silicon.
This appears to be related to Atmel Errata Reference 12015 (see § 35.4.1 DSU in the datasheet) but only applies to revision B silicon - not revision C. While this is an old silicion revision (latest is revision E as of 17 Jan 2015) I found one on a development board.
This commit is contained in:
Richard Meadows
parent
abcc04d4f3
commit
cad30cfa39
131
src/samd20.c
131
src/samd20.c
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@ -198,6 +198,51 @@ static const char samd20_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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#define CORTEXM_DHCSR_C_HALT (1 << 1)
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#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0)
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/* -------------------------------------------------------------------------- */
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/* Cortex-M definitions for SAM D20 revision B fix */
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/* -------------------------------------------------------------------------- */
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#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000)
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/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */
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#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000)
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#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004)
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#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008 + (4*(i)))
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#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000)
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#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000)
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#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020 + (0x10*(i)))
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#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024 + (0x10*(i)))
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#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028 + (0x10*(i)))
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#define CORTEXM_MAX_WATCHPOINTS 4 /* architecture says up to 15, no implementation has > 4 */
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#define CORTEXM_MAX_BREAKPOINTS 6 /* architecture says up to 127, no implementation has > 6 */
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struct cortexm_priv {
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bool stepping;
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bool on_bkpt;
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/* Watchpoint unit status */
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struct wp_unit_s {
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uint32_t addr;
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uint8_t type;
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uint8_t size;
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} hw_watchpoint[CORTEXM_MAX_WATCHPOINTS];
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unsigned hw_watchpoint_max;
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/* Breakpoint unit status */
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uint32_t hw_breakpoint[CORTEXM_MAX_BREAKPOINTS];
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unsigned hw_breakpoint_max;
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/* Copy of DEMCR for vector-catch */
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uint32_t demcr;
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/* Semihosting state */
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uint32_t syscall;
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uint32_t errno;
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uint32_t byte_count;
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};
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/* Utility */
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#define MINIMUM(a,b) ((a < b) ? a : b)
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@ -285,6 +330,81 @@ samd20_reset(struct target_s *target)
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target_check_error(target);
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}
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/**
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* Overloads the default cortexm detached function with a version that
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* removes the target from extended reset where required.
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*
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* Only required for SAM D20 _Revision B_ Silicon
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*/
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static void
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samd20_revB_detach(struct target_s *target)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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struct cortexm_priv *priv = ap->priv;
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unsigned i;
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/* Clear any stale breakpoints */
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for(i = 0; i < priv->hw_breakpoint_max; i++)
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adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), 0);
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/* Clear any stale watchpoints */
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for(i = 0; i < priv->hw_watchpoint_max; i++)
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adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), 0);
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/* Disable debug */
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adiv5_ap_mem_write(ap, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY);
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/* ---- Additional ---- */
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/* Exit extended reset */
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if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) &
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SAMD20_STATUSA_CRSTEXT) {
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/* Write bit to clear from extended reset */
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adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT,
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SAMD20_STATUSA_CRSTEXT);
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}
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}
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/**
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* Overloads the default cortexm halt_resume function with a version
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* that removes the target from extended reset where required.
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*
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* Only required for SAM D20 _Revision B_ Silicon
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*/
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static void
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samd20_revB_halt_resume(struct target_s *target, bool step)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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struct cortexm_priv *priv = ap->priv;
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uint32_t dhcsr = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN;
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if(step) dhcsr |= CORTEXM_DHCSR_C_STEP | CORTEXM_DHCSR_C_MASKINTS;
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/* Disable interrupts while single stepping... */
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if(step != priv->stepping) {
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adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr | CORTEXM_DHCSR_C_HALT);
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priv->stepping = step;
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}
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if (priv->on_bkpt) {
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uint32_t pc = target->pc_read(target);
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if ((adiv5_ap_mem_read_halfword(ap, pc) & 0xFF00) == 0xBE00)
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target->pc_write(target, pc + 2);
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}
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adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr);
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ap->dp->allow_timeout = true;
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/* ---- Additional ---- */
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/* Exit extended reset */
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if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) &
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SAMD20_STATUSA_CRSTEXT) {
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/* Write bit to clear from extended reset */
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adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT,
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SAMD20_STATUSA_CRSTEXT);
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}
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}
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char variant_string[30];
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bool samd20_probe(struct target_s *target)
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{
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@ -329,6 +449,17 @@ bool samd20_probe(struct target_s *target)
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/* Setup Target */
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target->driver = variant_string;
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target->reset = samd20_reset;
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if (revision_variant == 'B') {
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/**
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* These functions check for and
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* extended reset. Appears to be
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* related to Errata 35.4.1 ref 12015
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*/
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target->detach = samd20_revB_detach;
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target->halt_resume = samd20_revB_halt_resume;
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}
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target->xml_mem_map = samd20_xml_memory_map;
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target->flash_erase = samd20_flash_erase;
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target->flash_write = samd20_flash_write;
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