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stm32l0: Added some links to the reference manuals

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dragonmux 2022-07-12 20:36:14 -04:00 committed by Piotr Esden-Tempski
parent a22d6e5056
commit ce94169099
1 changed files with 44 additions and 43 deletions
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src/target/stm32l0.c
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@ -17,60 +17,61 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
/* Description /*
----------- Description
-----------
This is an implementation of the target-specific functions for the This is an implementation of the target-specific functions for the
STM32L0x[1] and STM32L1x[2] families of ST Microelectronics MCUs, STM32L0x[1] and STM32L1x[2] families of ST Microelectronics MCUs,
Cortex M0+ SOCs. The NVM interface is substantially similar to the Cortex M0+ SOCs. The NVM interface is substantially similar to the
STM32L1x parts. This module is written to better generalize the STM32L1x parts. This module is written to better generalize the
NVM interface and to provide more features. NVM interface and to provide more features.
[1] ST Microelectronics Document RM0377 (DocID025942), "Reference [1] ST Microelectronics Document RM0377 (DocID025942), "Reference
manual for Ultra-low-power STM32L0x1 advanced ARM-based 32-bit manual for Ultra-low-power STM32L0x1 advanced ARM-based 32-bit
MCUs," April 2014. MCUs," April 2014.
(https://www.st.com/resource/en/reference_manual/rm0377-ultralowpower-stm32l0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf)
[2] ST Microelectronics Document RM0038 (DocID15965, "..."Reference [2] ST Microelectronics Document RM0038 (DocID15965, "..."Reference
manual for STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx manual for STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx
advanced ARM®-based 32-bit MCUs, " July 2014 advanced ARM®-based 32-bit MCUs, " July 2014
(https://www.st.com/resource/en/reference_manual/rm0038-stm32l100xx-stm32l151xx-stm32l152xx-and-stm32l162xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf)
NOTES
=====
NOTES o Mass erase unimplemented. The method for performing a mass erase
===== is to set the options for read protection, reload the option
bytes, set options for no protection, and then reload the option
bytes again. The command fails because we lose contact with the
target when we perform the option byte reload. For the time
being, the command is disabled.
o Mass erase unimplemented. The method for performing a mass erase The body of the function was the following. It is left here for
is to set the options for read protection, reload the option reference in case someone either discovers what is wrong with
bytes, set options for no protection, and then reload the option these lines, or a change is made to the emulator that allows it
bytes again. The command fails because we lose contact with the to regain control of the target after the option byte reload.
target when we perform the option byte reload. For the time
being, the command is disabled.
The body of the function was the following. It is left here for stm32l0_option_write(t, 0x1ff80000, 0xffff0000);
reference in case someone either discovers what is wrong with target_mem_write32(target, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH);
these lines, or a change is made to the emulator that allows it stm32l0_option_write(t, 0x1ff80000, 0xff5500aa);
to regain control of the target after the option byte reload. target_mem_write32(target, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH);
stm32l0_option_write(t, 0x1ff80000, 0xffff0000); uint32_t sr;
target_mem_write32(target, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); do {
stm32l0_option_write(t, 0x1ff80000, 0xff5500aa); sr = target_mem_read32(target, STM32L0_NVM_SR);
target_mem_write32(target, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); } while (sr & STM32L0_NVM_SR_BSY);
uint32_t sr; o Errors. We probably should clear SR errors immediately after
do { detecting them. If we don't then we always must wait for the NVM
sr = target_mem_read32(target, STM32L0_NVM_SR); module to complete the last operation before we can start another.
} while (sr & STM32L0_NVM_SR_BSY);
o Errors. We probably should clear SR errors immediately after o There are minor inconsistencies between the stm32l0 and the
detecting them. If we don't then we always must wait for the NVM stm32l1 in when handling NVM operations.
module to complete the last operation before we can start another.
o There are minor inconsistencies between the stm32l0 and the
stm32l1 in when handling NVM operations.
o On the STM32L1xx, PECR can only be changed when the NVM
hardware is idle. The STM32L0xx allows the PECR to be updated
while an operation is in progress.
o On the STM32L1xx, PECR can only be changed when the NVM
hardware is idle. The STM32L0xx allows the PECR to be updated
while an operation is in progress.
*/ */
#include "general.h" #include "general.h"