target/adiv5: clang format/tidy
This commit is contained in:
Rafael Silva
Rachel Mant
parent
37efd257e8
commit
d1fa50336e
|
|
@ -44,10 +44,10 @@
|
|||
#define ARM_AP_TYPE_AHB5 5
|
||||
|
||||
/* ROM table CIDR values */
|
||||
#define CIDR0_OFFSET 0xFF0 /* DBGCID0 */
|
||||
#define CIDR1_OFFSET 0xFF4 /* DBGCID1 */
|
||||
#define CIDR2_OFFSET 0xFF8 /* DBGCID2 */
|
||||
#define CIDR3_OFFSET 0xFFC /* DBGCID3 */
|
||||
#define CIDR0_OFFSET 0xFF0 /* DBGCID0 */
|
||||
#define CIDR1_OFFSET 0xFF4 /* DBGCID1 */
|
||||
#define CIDR2_OFFSET 0xFF8 /* DBGCID2 */
|
||||
#define CIDR3_OFFSET 0xFFC /* DBGCID3 */
|
||||
|
||||
/* Component class ID register can be broken down into the following logical
|
||||
* interpretation of the 32bit value consisting of the least significant bytes
|
||||
|
|
@ -63,9 +63,10 @@
|
|||
* V
|
||||
* Component ID
|
||||
*/
|
||||
#define CID_PREAMBLE 0xB105000D
|
||||
#define CID_CLASS_MASK 0x0000F000
|
||||
#define CID_CLASS_SHIFT 12
|
||||
#define CID_PREAMBLE 0xB105000DUL
|
||||
#define CID_CLASS_MASK 0x0000F000UL
|
||||
#define CID_CLASS_SHIFT 12UL
|
||||
|
||||
/* The following enum is based on the Component Class value table 13-3 of the
|
||||
* ADIv5 standard.
|
||||
*/
|
||||
|
|
@ -85,40 +86,39 @@ enum cid_class {
|
|||
|
||||
#ifdef ENABLE_DEBUG
|
||||
/* The reserved ones only have an R in them, to save a bit of space. */
|
||||
static const char * const cidc_debug_strings[] =
|
||||
{
|
||||
[cidc_gvc] = "Generic verification component", /* 0x0 */
|
||||
[cidc_romtab] = "ROM Table", /* 0x1 */
|
||||
[0x2 ... 0x8] = "R", /* 0x2 - 0x8 */
|
||||
[cidc_dc] = "Debug component", /* 0x9 */
|
||||
[0xA] = "R", /* 0xA */
|
||||
[cidc_ptb] = "Peripheral Test Block", /* 0xB */
|
||||
[0xC] = "R", /* 0xC */
|
||||
[cidc_dess] = "OptimoDE Data Engine SubSystem component", /* 0xD */
|
||||
[cidc_gipc] = "Generic IP component", /* 0xE */
|
||||
[cidc_pcp] = "PrimeCell peripheral", /* 0xF */
|
||||
[cidc_unknown] = "Unknown component class" /* 0x10 */
|
||||
static const char *const cidc_debug_strings[] = {
|
||||
[cidc_gvc] = "Generic verification component", /* 0x0 */
|
||||
[cidc_romtab] = "ROM Table", /* 0x1 */
|
||||
[0x2 ... 0x8] = "R", /* 0x2 - 0x8 */
|
||||
[cidc_dc] = "Debug component", /* 0x9 */
|
||||
[0xA] = "R", /* 0xA */
|
||||
[cidc_ptb] = "Peripheral Test Block", /* 0xB */
|
||||
[0xC] = "R", /* 0xC */
|
||||
[cidc_dess] = "OptimoDE Data Engine SubSystem component", /* 0xD */
|
||||
[cidc_gipc] = "Generic IP component", /* 0xE */
|
||||
[cidc_pcp] = "PrimeCell peripheral", /* 0xF */
|
||||
[cidc_unknown] = "Unknown component class" /* 0x10 */
|
||||
};
|
||||
#endif
|
||||
|
||||
#define PIDR0_OFFSET 0xFE0 /* DBGPID0 */
|
||||
#define PIDR1_OFFSET 0xFE4 /* DBGPID1 */
|
||||
#define PIDR2_OFFSET 0xFE8 /* DBGPID2 */
|
||||
#define PIDR3_OFFSET 0xFEC /* DBGPID3 */
|
||||
#define PIDR4_OFFSET 0xFD0 /* DBGPID4 */
|
||||
#define PIDR5_OFFSET 0xFD4 /* DBGPID5 (Reserved) */
|
||||
#define PIDR6_OFFSET 0xFD8 /* DBGPID6 (Reserved) */
|
||||
#define PIDR7_OFFSET 0xFDC /* DBGPID7 (Reserved) */
|
||||
#define PIDR0_OFFSET 0xFE0 /* DBGPID0 */
|
||||
#define PIDR1_OFFSET 0xFE4 /* DBGPID1 */
|
||||
#define PIDR2_OFFSET 0xFE8 /* DBGPID2 */
|
||||
#define PIDR3_OFFSET 0xFEC /* DBGPID3 */
|
||||
#define PIDR4_OFFSET 0xFD0 /* DBGPID4 */
|
||||
#define PIDR5_OFFSET 0xFD4 /* DBGPID5 (Reserved) */
|
||||
#define PIDR6_OFFSET 0xFD8 /* DBGPID6 (Reserved) */
|
||||
#define PIDR7_OFFSET 0xFDC /* DBGPID7 (Reserved) */
|
||||
#define PIDR_REV_MASK 0x0FFF00000ULL /* Revision bits. */
|
||||
#define PIDR_PN_MASK 0x000000FFFULL /* Part number bits. */
|
||||
#define PIDR_ARM_BITS 0x4000BB000ULL /* These make up the ARM JEP-106 code. */
|
||||
|
||||
#define DEVTYPE_OFFSET 0xFCC /* CoreSight Device Type Register */
|
||||
#define DEVARCH_OFFSET 0xFBC /* CoreSight Device Architecture Register */
|
||||
#define DEVTYPE_OFFSET 0xFCCU /* CoreSight Device Type Register */
|
||||
#define DEVARCH_OFFSET 0xFBCU /* CoreSight Device Architecture Register */
|
||||
|
||||
#define DEVTYPE_MASK 0x000000FF
|
||||
#define DEVARCH_PRESENT (1u << 20)
|
||||
#define DEVARCH_ARCHID_MASK 0x0000FFFF
|
||||
#define DEVTYPE_MASK 0x000000FFU
|
||||
#define DEVARCH_PRESENT (1U << 20)
|
||||
#define DEVARCH_ARCHID_MASK 0x0000FFFFU
|
||||
|
||||
enum arm_arch {
|
||||
aa_nosupport,
|
||||
|
|
@ -187,80 +187,89 @@ static const struct {
|
|||
const char *full;
|
||||
#endif
|
||||
} pidr_pn_bits[] = {
|
||||
{0x000, 0x00, 0, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M3 SCS", "(System Control Space)")},
|
||||
{0x001, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 ITM", "(Instrumentation Trace Module)")},
|
||||
{0x002, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 DWT", "(Data Watchpoint and Trace)")},
|
||||
{0x003, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 FBP", "(Flash Patch and Breakpoint)")},
|
||||
{0x008, 0x00, 0, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M0 SCS", "(System Control Space)")},
|
||||
{0x00a, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0 DWT", "(Data Watchpoint and Trace)")},
|
||||
{0x00b, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0 BPU", "(Breakpoint Unit)")},
|
||||
{0x00c, 0x00, 0, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M4 SCS", "(System Control Space)")},
|
||||
{0x00d, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM11", "(Embedded Trace)")},
|
||||
{0x00e, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 FBP", "(Flash Patch and Breakpoint)")},
|
||||
{0x101, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("System TSGEN", "(Time Stamp Generator)")},
|
||||
{0x471, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0 ROM", "(Cortex-M0 ROM)")},
|
||||
{0x490, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 GIC", "(Generic Interrupt Controller)")},
|
||||
{0x4c0, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0+ ROM", "(Cortex-M0+ ROM)")},
|
||||
{0x4c3, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 ROM", "(Cortex-M3 ROM)")},
|
||||
{0x4c4, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 ROM", "(Cortex-M4 ROM)")},
|
||||
{0x4c7, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 PPB", "(Cortex-M7 Private Peripheral Bus ROM Table)")},
|
||||
{0x4c8, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 ROM", "(Cortex-M7 ROM)")},
|
||||
{0x906, 0x14, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight CTI", "(Cross Trigger)")},
|
||||
{0x907, 0x21, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETB", "(Trace Buffer)")},
|
||||
{0x908, 0x12, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight CSTF", "(Trace Funnel)")},
|
||||
{0x910, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM9", "(Embedded Trace)")},
|
||||
{0x912, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TPIU", "(Trace Port Interface Unit)")},
|
||||
{0x913, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ITM", "(Instrumentation Trace Macrocell)")},
|
||||
{0x914, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight SWO", "(Single Wire Output)")},
|
||||
{0x917, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight HTM", "(AHB Trace Macrocell)")},
|
||||
{0x920, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM11", "(Embedded Trace)")},
|
||||
{0x921, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A8 ETM", "(Embedded Trace)")},
|
||||
{0x922, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A8 CTI", "(Cross Trigger)")},
|
||||
{0x923, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 TPIU", "(Trace Port Interface Unit)")},
|
||||
{0x924, 0x13, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 ETM", "(Embedded Trace)")},
|
||||
{0x925, 0x13, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 ETM", "(Embedded Trace)")},
|
||||
{0x930, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-R4 ETM", "(Embedded Trace)")},
|
||||
{0x932, 0x31, 0x0a31, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight MTB-M0+", "(Simple Execution Trace)")},
|
||||
{0x941, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TPIU-Lite", "(Trace Port Interface Unit)")},
|
||||
{0x950, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight Component", "(unidentified Cortex-A9 component)")},
|
||||
{0x955, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight Component", "(unidentified Cortex-A5 component)")},
|
||||
{0x956, 0x13, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A7 ETM", "(Embedded Trace)")},
|
||||
{0x95f, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 PTM", "(Program Trace Macrocell)")},
|
||||
{0x961, 0x32, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TMC", "(Trace Memory Controller)")},
|
||||
{0x962, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight STM", "(System Trace Macrocell)")},
|
||||
{0x963, 0x63, 0x0a63, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight STM", "(System Trace Macrocell)")},
|
||||
{0x975, 0x13, 0x4a13, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 ETM", "(Embedded Trace)")},
|
||||
{0x9a0, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight PMU", "(Performance Monitoring Unit)")},
|
||||
{0x9a1, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 TPIU", "(Trace Port Interface Unit)")},
|
||||
{0x9a6, 0x14, 0x1a14, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M0+ CTI", "(Cross Trigger Interface)")},
|
||||
{0x9a9, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 TPIU", "(Trace Port Interface Unit)")},
|
||||
{0x9a5, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A5 ETM", "(Embedded Trace)")},
|
||||
{0x9a7, 0x16, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A7 PMU", "(Performance Monitor Unit)")},
|
||||
{0x9af, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 PMU", "(Performance Monitor Unit)")},
|
||||
{0xc05, 0x00, 0, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A5 Debug", "(Debug Unit)")},
|
||||
{0xc07, 0x15, 0, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A7 Debug", "(Debug Unit)")},
|
||||
{0xc08, 0x00, 0, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A8 Debug", "(Debug Unit)")},
|
||||
{0xc09, 0x00, 0, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A9 Debug", "(Debug Unit)")},
|
||||
{0xc0f, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 Debug", "(Debug Unit)")}, /* support? */
|
||||
{0xc14, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-R4 Debug", "(Debug Unit)")}, /* support? */
|
||||
{0xcd0, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Atmel DSU", "(Device Service Unit)")},
|
||||
{0xd20, 0x00, 0x2a04, aa_cortexm, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(System Control Space)")},
|
||||
{0xd20, 0x11, 0, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Trace Port Interface Unit)")},
|
||||
{0xd20, 0x13, 0, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Embedded Trace)")},
|
||||
{0xd20, 0x31, 0x0a31, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Micro Trace Buffer)")},
|
||||
{0xd20, 0x00, 0x1a02, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Data Watchpoint and Trace)")},
|
||||
{0xd20, 0x00, 0x1a03, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Breakpoint Unit)")},
|
||||
{0xd20, 0x14, 0x1a14, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Cross Trigger)")},
|
||||
{0xd21, 0x00, 0x2a04, aa_cortexm, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(System Control Space)")},
|
||||
{0xd21, 0x31, 0x0a31, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Micro Trace Buffer)")},
|
||||
{0xd21, 0x43, 0x1a01, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Instrumentation Trace Macrocell)")},
|
||||
{0xd21, 0x00, 0x1a02, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Data Watchpoint and Trace)")},
|
||||
{0xd21, 0x00, 0x1a03, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Breakpoint Unit)")},
|
||||
{0xd21, 0x14, 0x1a14, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Cross Trigger)")},
|
||||
{0xd21, 0x13, 0x4a13, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Embedded Trace)")},
|
||||
{0xd21, 0x11, 0, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Trace Port Interface Unit)")},
|
||||
{0xfff, 0x00, 0, aa_end, cidc_unknown, PIDR_PN_BIT_STRINGS("end", "end")}
|
||||
};
|
||||
{0x000, 0x00, 0, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M3 SCS", "(System Control Space)")},
|
||||
{0x001, 0x00, 0, aa_nosupport, cidc_unknown,
|
||||
PIDR_PN_BIT_STRINGS("Cortex-M3 ITM", "(Instrumentation Trace Module)")},
|
||||
{0x002, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 DWT", "(Data Watchpoint and Trace)")},
|
||||
{0x003, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 FBP", "(Flash Patch and Breakpoint)")},
|
||||
{0x008, 0x00, 0, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M0 SCS", "(System Control Space)")},
|
||||
{0x00a, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0 DWT", "(Data Watchpoint and Trace)")},
|
||||
{0x00b, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0 BPU", "(Breakpoint Unit)")},
|
||||
{0x00c, 0x00, 0, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M4 SCS", "(System Control Space)")},
|
||||
{0x00d, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM11", "(Embedded Trace)")},
|
||||
{0x00e, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 FBP", "(Flash Patch and Breakpoint)")},
|
||||
{0x101, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("System TSGEN", "(Time Stamp Generator)")},
|
||||
{0x471, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0 ROM", "(Cortex-M0 ROM)")},
|
||||
{0x490, 0x00, 0, aa_nosupport, cidc_unknown,
|
||||
PIDR_PN_BIT_STRINGS("Cortex-A15 GIC", "(Generic Interrupt Controller)")},
|
||||
{0x4c0, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0+ ROM", "(Cortex-M0+ ROM)")},
|
||||
{0x4c3, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 ROM", "(Cortex-M3 ROM)")},
|
||||
{0x4c4, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 ROM", "(Cortex-M4 ROM)")},
|
||||
{0x4c7, 0x00, 0, aa_nosupport, cidc_unknown,
|
||||
PIDR_PN_BIT_STRINGS("Cortex-M7 PPB", "(Cortex-M7 Private Peripheral Bus ROM Table)")},
|
||||
{0x4c8, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 ROM", "(Cortex-M7 ROM)")},
|
||||
{0x906, 0x14, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight CTI", "(Cross Trigger)")},
|
||||
{0x907, 0x21, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETB", "(Trace Buffer)")},
|
||||
{0x908, 0x12, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight CSTF", "(Trace Funnel)")},
|
||||
{0x910, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM9", "(Embedded Trace)")},
|
||||
{0x912, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TPIU", "(Trace Port Interface Unit)")},
|
||||
{0x913, 0x00, 0, aa_nosupport, cidc_unknown,
|
||||
PIDR_PN_BIT_STRINGS("CoreSight ITM", "(Instrumentation Trace Macrocell)")},
|
||||
{0x914, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight SWO", "(Single Wire Output)")},
|
||||
{0x917, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight HTM", "(AHB Trace Macrocell)")},
|
||||
{0x920, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM11", "(Embedded Trace)")},
|
||||
{0x921, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A8 ETM", "(Embedded Trace)")},
|
||||
{0x922, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A8 CTI", "(Cross Trigger)")},
|
||||
{0x923, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 TPIU", "(Trace Port Interface Unit)")},
|
||||
{0x924, 0x13, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 ETM", "(Embedded Trace)")},
|
||||
{0x925, 0x13, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 ETM", "(Embedded Trace)")},
|
||||
{0x930, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-R4 ETM", "(Embedded Trace)")},
|
||||
{0x932, 0x31, 0x0a31, aa_nosupport, cidc_unknown,
|
||||
PIDR_PN_BIT_STRINGS("CoreSight MTB-M0+", "(Simple Execution Trace)")},
|
||||
{0x941, 0x00, 0, aa_nosupport, cidc_unknown,
|
||||
PIDR_PN_BIT_STRINGS("CoreSight TPIU-Lite", "(Trace Port Interface Unit)")},
|
||||
{0x950, 0x00, 0, aa_nosupport, cidc_unknown,
|
||||
PIDR_PN_BIT_STRINGS("CoreSight Component", "(unidentified Cortex-A9 component)")},
|
||||
{0x955, 0x00, 0, aa_nosupport, cidc_unknown,
|
||||
PIDR_PN_BIT_STRINGS("CoreSight Component", "(unidentified Cortex-A5 component)")},
|
||||
{0x956, 0x13, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A7 ETM", "(Embedded Trace)")},
|
||||
{0x95f, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 PTM", "(Program Trace Macrocell)")},
|
||||
{0x961, 0x32, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TMC", "(Trace Memory Controller)")},
|
||||
{0x962, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight STM", "(System Trace Macrocell)")},
|
||||
{0x963, 0x63, 0x0a63, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight STM", "(System Trace Macrocell)")},
|
||||
{0x975, 0x13, 0x4a13, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 ETM", "(Embedded Trace)")},
|
||||
{0x9a0, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight PMU", "(Performance Monitoring Unit)")},
|
||||
{0x9a1, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 TPIU", "(Trace Port Interface Unit)")},
|
||||
{0x9a6, 0x14, 0x1a14, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M0+ CTI", "(Cross Trigger Interface)")},
|
||||
{0x9a9, 0x11, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 TPIU", "(Trace Port Interface Unit)")},
|
||||
{0x9a5, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A5 ETM", "(Embedded Trace)")},
|
||||
{0x9a7, 0x16, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A7 PMU", "(Performance Monitor Unit)")},
|
||||
{0x9af, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 PMU", "(Performance Monitor Unit)")},
|
||||
{0xc05, 0x00, 0, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A5 Debug", "(Debug Unit)")},
|
||||
{0xc07, 0x15, 0, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A7 Debug", "(Debug Unit)")},
|
||||
{0xc08, 0x00, 0, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A8 Debug", "(Debug Unit)")},
|
||||
{0xc09, 0x00, 0, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A9 Debug", "(Debug Unit)")},
|
||||
{0xc0f, 0x00, 0, aa_nosupport, cidc_unknown,
|
||||
PIDR_PN_BIT_STRINGS("Cortex-A15 Debug", "(Debug Unit)")}, /* support? */
|
||||
{0xc14, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-R4 Debug", "(Debug Unit)")}, /* support? */
|
||||
{0xcd0, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Atmel DSU", "(Device Service Unit)")},
|
||||
{0xd20, 0x00, 0x2a04, aa_cortexm, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(System Control Space)")},
|
||||
{0xd20, 0x11, 0, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Trace Port Interface Unit)")},
|
||||
{0xd20, 0x13, 0, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Embedded Trace)")},
|
||||
{0xd20, 0x31, 0x0a31, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Micro Trace Buffer)")},
|
||||
{0xd20, 0x00, 0x1a02, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Data Watchpoint and Trace)")},
|
||||
{0xd20, 0x00, 0x1a03, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Breakpoint Unit)")},
|
||||
{0xd20, 0x14, 0x1a14, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M23", "(Cross Trigger)")},
|
||||
{0xd21, 0x00, 0x2a04, aa_cortexm, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(System Control Space)")},
|
||||
{0xd21, 0x31, 0x0a31, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Micro Trace Buffer)")},
|
||||
{0xd21, 0x43, 0x1a01, aa_nosupport, cidc_dc,
|
||||
PIDR_PN_BIT_STRINGS("Cortex-M33", "(Instrumentation Trace Macrocell)")},
|
||||
{0xd21, 0x00, 0x1a02, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Data Watchpoint and Trace)")},
|
||||
{0xd21, 0x00, 0x1a03, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Breakpoint Unit)")},
|
||||
{0xd21, 0x14, 0x1a14, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Cross Trigger)")},
|
||||
{0xd21, 0x13, 0x4a13, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Embedded Trace)")},
|
||||
{0xd21, 0x11, 0, aa_nosupport, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-M33", "(Trace Port Interface Unit)")},
|
||||
{0xfff, 0x00, 0, aa_end, cidc_unknown, PIDR_PN_BIT_STRINGS("end", "end")}};
|
||||
|
||||
extern bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base);
|
||||
|
||||
|
|
@ -306,7 +315,7 @@ static uint32_t adiv5_ap_read_id(ADIv5_AP_t *ap, uint32_t addr)
|
|||
uint64_t adiv5_ap_read_pidr(ADIv5_AP_t *ap, uint32_t addr)
|
||||
{
|
||||
uint64_t pidr = adiv5_ap_read_id(ap, addr + PIDR4_OFFSET);
|
||||
pidr = pidr << 32 | adiv5_ap_read_id(ap, addr + PIDR0_OFFSET);
|
||||
pidr = pidr << 32 | adiv5_ap_read_id(ap, addr + PIDR0_OFFSET);
|
||||
return pidr;
|
||||
}
|
||||
|
||||
|
|
@ -318,11 +327,10 @@ uint64_t adiv5_ap_read_pidr(ADIv5_AP_t *ap, uint32_t addr)
|
|||
*/
|
||||
static uint32_t cortexm_initial_halt(ADIv5_AP_t *ap)
|
||||
{
|
||||
platform_timeout to ;
|
||||
platform_timeout to;
|
||||
uint32_t ctrlstat = adiv5_dp_read(ap->dp, ADIV5_DP_CTRLSTAT);
|
||||
platform_timeout_set(&to, cortexm_wait_timeout);
|
||||
uint32_t dhcsr_ctl = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN |
|
||||
CORTEXM_DHCSR_C_HALT;
|
||||
uint32_t dhcsr_ctl = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN | CORTEXM_DHCSR_C_HALT;
|
||||
uint32_t dhcsr_valid = CORTEXM_DHCSR_S_HALT | CORTEXM_DHCSR_C_DEBUGEN;
|
||||
bool reset_seen = false;
|
||||
bool use_low_access = (!(ap->dp->idcode & ADIV5_MINDP));
|
||||
|
|
@ -331,28 +339,26 @@ static uint32_t cortexm_initial_halt(ADIv5_AP_t *ap)
|
|||
adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD);
|
||||
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, CORTEXM_DHCSR);
|
||||
}
|
||||
/* Workaround for CMSIS-DAP Bulk orbtrace
|
||||
* High values of TRNCNT lead to NO_ACK answer from debugger.
|
||||
*
|
||||
* However CMSIS/HID even with highest value has few chances to catch
|
||||
* a STM32F767 mostly sleeping in WFI!
|
||||
*/
|
||||
/* Workaround for CMSIS-DAP Bulk orbtrace
|
||||
* High values of TRNCNT lead to NO_ACK answer from debugger.
|
||||
*
|
||||
* However CMSIS/HID even with highest value has few chances to catch
|
||||
* a STM32F767 mostly sleeping in WFI!
|
||||
*/
|
||||
uint32_t start_time = platform_time_ms();
|
||||
int trncnt = 0x80;
|
||||
while (!platform_timeout_is_expired(&to)) {
|
||||
uint32_t dhcsr ;
|
||||
uint32_t dhcsr;
|
||||
if (use_low_access) {
|
||||
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_DP_CTRLSTAT,
|
||||
ctrlstat | (trncnt * ADIV5_DP_CTRLSTAT_TRNCNT));
|
||||
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW,
|
||||
dhcsr_ctl);
|
||||
adiv5_dp_low_access(
|
||||
ap->dp, ADIV5_LOW_WRITE, ADIV5_DP_CTRLSTAT, ctrlstat | (trncnt * ADIV5_DP_CTRLSTAT_TRNCNT));
|
||||
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW, dhcsr_ctl);
|
||||
if (trncnt < 0xfff) {
|
||||
trncnt += (platform_time_ms() - start_time) * 8;
|
||||
trncnt += (platform_time_ms() - start_time) * 8;
|
||||
} else {
|
||||
trncnt = 0xfff;
|
||||
}
|
||||
dhcsr = adiv5_dp_low_access(
|
||||
ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0);
|
||||
dhcsr = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0);
|
||||
} else {
|
||||
adiv5_mem_write(ap, CORTEXM_DHCSR, &dhcsr_ctl, sizeof(dhcsr_ctl));
|
||||
dhcsr = adiv5_mem_read32(ap, CORTEXM_DHCSR);
|
||||
|
|
@ -363,9 +369,9 @@ static uint32_t cortexm_initial_halt(ADIv5_AP_t *ap)
|
|||
* 0x0xA05F0000 may happen.
|
||||
* M23/33 will have S_SDE set when debug is allowed
|
||||
*/
|
||||
if ((dhcsr != 0xffffffff) && /* Invalid read */
|
||||
((dhcsr & 0xf000fff0) == 0)) {/* Check RAZ bits */
|
||||
if ((dhcsr & CORTEXM_DHCSR_S_RESET_ST) && !reset_seen) {
|
||||
if ((dhcsr != 0xffffffff) && /* Invalid read */
|
||||
((dhcsr & 0xf000fff0) == 0)) { /* Check RAZ bits */
|
||||
if ((dhcsr & CORTEXM_DHCSR_S_RESET_ST) && !reset_seen) {
|
||||
if (connect_assert_nrst)
|
||||
return dhcsr;
|
||||
reset_seen = true;
|
||||
|
|
@ -400,26 +406,21 @@ static uint32_t cortexm_initial_halt(ADIv5_AP_t *ap)
|
|||
*/
|
||||
static bool cortexm_prepare(ADIv5_AP_t *ap)
|
||||
{
|
||||
#if ((PC_HOSTED == 1) || (ENABLE_DEBUG == 1))
|
||||
#if ((PC_HOSTED == 1) || (ENABLE_DEBUG == 1))
|
||||
uint32_t start_time = platform_time_ms();
|
||||
#endif
|
||||
uint32_t dhcsr = cortexm_initial_halt(ap);
|
||||
if (!dhcsr) {
|
||||
DEBUG_WARN("Halt via DHCSR: Failure DHCSR %08" PRIx32 " after % "
|
||||
PRId32 "ms\nTry again, evt. with longer timeout or "
|
||||
"connect under reset\n",
|
||||
adiv5_mem_read32(ap, CORTEXM_DHCSR),
|
||||
platform_time_ms() - start_time);
|
||||
DEBUG_WARN("Halt via DHCSR: Failure DHCSR %08" PRIx32 " after % " PRId32 "ms\nTry again, evt. with longer "
|
||||
"timeout or connect under reset\n",
|
||||
adiv5_mem_read32(ap, CORTEXM_DHCSR), platform_time_ms() - start_time);
|
||||
return false;
|
||||
}
|
||||
DEBUG_INFO("Halt via DHCSR: success %08" PRIx32 " after %" PRId32 "ms\n",
|
||||
dhcsr,
|
||||
platform_time_ms() - start_time);
|
||||
DEBUG_INFO("Halt via DHCSR: success %08" PRIx32 " after %" PRId32 "ms\n", dhcsr, platform_time_ms() - start_time);
|
||||
ap->ap_cortexm_demcr = adiv5_mem_read32(ap, CORTEXM_DEMCR);
|
||||
uint32_t demcr = CORTEXM_DEMCR_TRCENA | CORTEXM_DEMCR_VC_HARDERR |
|
||||
CORTEXM_DEMCR_VC_CORERESET;
|
||||
uint32_t demcr = CORTEXM_DEMCR_TRCENA | CORTEXM_DEMCR_VC_HARDERR | CORTEXM_DEMCR_VC_CORERESET;
|
||||
adiv5_mem_write(ap, CORTEXM_DEMCR, &demcr, sizeof(demcr));
|
||||
platform_timeout to ;
|
||||
platform_timeout to;
|
||||
platform_timeout_set(&to, cortexm_wait_timeout);
|
||||
platform_nrst_set_val(false);
|
||||
while (1) {
|
||||
|
|
@ -437,9 +438,9 @@ static bool cortexm_prepare(ADIv5_AP_t *ap)
|
|||
/* Return true if we find a debuggable device.*/
|
||||
static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion, int num_entry)
|
||||
{
|
||||
(void) num_entry;
|
||||
(void)num_entry;
|
||||
addr &= 0xfffff000; /* Mask out base address */
|
||||
if (addr == 0) /* No rom table on this AP */
|
||||
if (addr == 0) /* No rom table on this AP */
|
||||
return;
|
||||
volatile uint32_t cidr;
|
||||
cidr = adiv5_ap_read_id(ap, addr + CIDR0_OFFSET);
|
||||
|
|
@ -448,11 +449,12 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
|
|||
return;
|
||||
}
|
||||
if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE)
|
||||
return;
|
||||
return;
|
||||
#if defined(ENABLE_DEBUG)
|
||||
char indent[recursion + 1];
|
||||
|
||||
for(int i = 0; i < recursion; i++) indent[i] = ' ';
|
||||
for (int i = 0; i < recursion; i++)
|
||||
indent[i] = ' ';
|
||||
indent[recursion] = 0;
|
||||
#endif
|
||||
|
||||
|
|
@ -463,9 +465,8 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
|
|||
|
||||
/* CIDR preamble sanity check */
|
||||
if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) {
|
||||
DEBUG_WARN("%s%d 0x%08" PRIx32": 0x%08" PRIx32
|
||||
" <- does not match preamble (0x%X)\n",
|
||||
indent + 1, num_entry, addr, cidr, CID_PREAMBLE);
|
||||
DEBUG_WARN("%s%d 0x%08" PRIx32 ": 0x%08" PRIx32 " <- does not match preamble (0x%X)\n", indent + 1, num_entry,
|
||||
addr, cidr, CID_PREAMBLE);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -479,23 +480,21 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
|
|||
uint16_t partno = pidr & 0xfff;
|
||||
#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
|
||||
/* Check SYSMEM bit */
|
||||
uint32_t memtype = adiv5_mem_read32(ap, addr | ADIV5_ROM_MEMTYPE) &
|
||||
ADIV5_ROM_MEMTYPE_SYSMEM;
|
||||
uint32_t memtype = adiv5_mem_read32(ap, addr | ADIV5_ROM_MEMTYPE) & ADIV5_ROM_MEMTYPE_SYSMEM;
|
||||
|
||||
if (adiv5_dp_error(ap->dp)) {
|
||||
DEBUG_WARN("Fault reading ROM table entry\n");
|
||||
}
|
||||
|
||||
DEBUG_INFO("ROM: Table BASE=0x%" PRIx32 " SYSMEM=0x%08" PRIx32
|
||||
", designer %3x Partno %3x\n", addr, memtype, designer,
|
||||
partno);
|
||||
DEBUG_INFO("ROM: Table BASE=0x%" PRIx32 " SYSMEM=0x%08" PRIx32 ", designer %3x Partno %3x\n", addr, memtype,
|
||||
designer, partno);
|
||||
#endif
|
||||
if (recursion == 0) {
|
||||
ap->ap_designer = designer;
|
||||
ap->ap_partno = partno;
|
||||
ap->ap_partno = partno;
|
||||
if ((ap->ap_designer == AP_DESIGNER_ATMEL) && (ap->ap_partno == 0xcd0)) {
|
||||
#define SAMX5X_DSU_CTRLSTAT 0x41002100
|
||||
#define SAMX5X_STATUSB_PROT (1 << 16)
|
||||
#define SAMX5X_DSU_CTRLSTAT 0x41002100
|
||||
#define SAMX5X_STATUSB_PROT (1 << 16)
|
||||
uint32_t ctrlstat = adiv5_mem_read32(ap, SAMX5X_DSU_CTRLSTAT);
|
||||
if (ctrlstat & SAMX5X_STATUSB_PROT) {
|
||||
/* A protected SAMx5x device is found.
|
||||
|
|
@ -509,7 +508,7 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
|
|||
}
|
||||
for (int i = 0; i < 960; i++) {
|
||||
adiv5_dp_error(ap->dp);
|
||||
uint32_t entry = adiv5_mem_read32(ap, addr + i*4);
|
||||
uint32_t entry = adiv5_mem_read32(ap, addr + i * 4);
|
||||
if (adiv5_dp_error(ap->dp)) {
|
||||
DEBUG_WARN("%sFault reading ROM table entry %d\n", indent, i);
|
||||
break;
|
||||
|
|
@ -519,15 +518,12 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
|
|||
break;
|
||||
|
||||
if (!(entry & ADIV5_ROM_ROMENTRY_PRESENT)) {
|
||||
DEBUG_INFO("%s%d Entry 0x%" PRIx32 " -> Not present\n", indent,
|
||||
i, entry);
|
||||
DEBUG_INFO("%s%d Entry 0x%" PRIx32 " -> Not present\n", indent, i, entry);
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Probe recursively */
|
||||
adiv5_component_probe(
|
||||
ap, addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET),
|
||||
recursion + 1, i);
|
||||
adiv5_component_probe(ap, addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET), recursion + 1, i);
|
||||
}
|
||||
DEBUG_INFO("%sROM: Table END\n", indent);
|
||||
} else {
|
||||
|
|
@ -535,9 +531,8 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
|
|||
* any components by other designers.
|
||||
*/
|
||||
if ((pidr & ~(PIDR_REV_MASK | PIDR_PN_MASK)) != PIDR_ARM_BITS) {
|
||||
DEBUG_WARN("%s0x%" PRIx32 ": 0x%02" PRIx32 "%08" PRIx32
|
||||
" <- does not match ARM JEP-106\n",
|
||||
indent, addr, (uint32_t)(pidr >> 32), (uint32_t)pidr);
|
||||
DEBUG_WARN("%s0x%" PRIx32 ": 0x%02" PRIx32 "%08" PRIx32 " <- does not match ARM JEP-106\n", indent, addr,
|
||||
(uint32_t)(pidr >> 32), (uint32_t)pidr);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -561,24 +556,18 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
|
|||
*/
|
||||
int i;
|
||||
for (i = 0; pidr_pn_bits[i].arch != aa_end; i++) {
|
||||
if ((pidr_pn_bits[i].part_number == part_number)
|
||||
&& (pidr_pn_bits[i].dev_type == dev_type)
|
||||
&& (pidr_pn_bits[i].arch_id == arch_id)) {
|
||||
DEBUG_INFO("%s%d 0x%" PRIx32 ": %s - %s %s (PIDR = 0x%02" PRIx32
|
||||
"%08" PRIx32 " DEVTYPE = 0x%02" PRIx8 " ARCHID = 0x%04" PRIx16 ")",
|
||||
indent + 1, num_entry, addr,
|
||||
cidc_debug_strings[cid_class],
|
||||
pidr_pn_bits[i].type, pidr_pn_bits[i].full,
|
||||
(uint32_t)(pidr >> 32), (uint32_t)pidr, dev_type, arch_id);
|
||||
if ((pidr_pn_bits[i].part_number == part_number) && (pidr_pn_bits[i].dev_type == dev_type) &&
|
||||
(pidr_pn_bits[i].arch_id == arch_id)) {
|
||||
DEBUG_INFO("%s%d 0x%" PRIx32 ": %s - %s %s (PIDR = 0x%02" PRIx32 "%08" PRIx32 " DEVTYPE = 0x%02" PRIx8
|
||||
" ARCHID = 0x%04" PRIx16 ")",
|
||||
indent + 1, num_entry, addr, cidc_debug_strings[cid_class], pidr_pn_bits[i].type,
|
||||
pidr_pn_bits[i].full, (uint32_t)(pidr >> 32), (uint32_t)pidr, dev_type, arch_id);
|
||||
/* Perform sanity check, if we know what to expect as
|
||||
* component ID class.
|
||||
*/
|
||||
if ((pidr_pn_bits[i].cidc != cidc_unknown) &&
|
||||
(cid_class != pidr_pn_bits[i].cidc)) {
|
||||
DEBUG_WARN("%sWARNING: \"%s\" !match expected \"%s\"\n",
|
||||
indent + 1,
|
||||
cidc_debug_strings[cid_class],
|
||||
cidc_debug_strings[pidr_pn_bits[i].cidc]);
|
||||
if ((pidr_pn_bits[i].cidc != cidc_unknown) && (cid_class != pidr_pn_bits[i].cidc)) {
|
||||
DEBUG_WARN("%sWARNING: \"%s\" !match expected \"%s\"\n", indent + 1, cidc_debug_strings[cid_class],
|
||||
cidc_debug_strings[pidr_pn_bits[i].cidc]);
|
||||
}
|
||||
switch (pidr_pn_bits[i].arch) {
|
||||
case aa_cortexm:
|
||||
|
|
@ -597,10 +586,9 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
|
|||
}
|
||||
}
|
||||
if (pidr_pn_bits[i].arch == aa_end) {
|
||||
DEBUG_WARN("%s0x%" PRIx32 ": %s - Unknown (PIDR = 0x%02" PRIx32
|
||||
"%08" PRIx32 " DEVTYPE = 0x%02" PRIx8 " ARCHID = 0x%04" PRIx16 ")\n",
|
||||
indent, addr, cidc_debug_strings[cid_class],
|
||||
(uint32_t)(pidr >> 32), (uint32_t)pidr, dev_type, arch_id);
|
||||
DEBUG_WARN("%s0x%" PRIx32 ": %s - Unknown (PIDR = 0x%02" PRIx32 "%08" PRIx32 " DEVTYPE = 0x%02" PRIx8
|
||||
" ARCHID = 0x%04" PRIx16 ")\n",
|
||||
indent, addr, cidc_debug_strings[cid_class], (uint32_t)(pidr >> 32), (uint32_t)pidr, dev_type, arch_id);
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
|
@ -624,20 +612,18 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
if(!tmpap.idr) /* IDR Invalid */
|
||||
if (!tmpap.idr) /* IDR Invalid */
|
||||
return NULL;
|
||||
tmpap.csw = adiv5_ap_read(&tmpap, ADIV5_AP_CSW) &
|
||||
~(ADIV5_AP_CSW_SIZE_MASK | ADIV5_AP_CSW_ADDRINC_MASK);
|
||||
tmpap.csw = adiv5_ap_read(&tmpap, ADIV5_AP_CSW) & ~(ADIV5_AP_CSW_SIZE_MASK | ADIV5_AP_CSW_ADDRINC_MASK);
|
||||
|
||||
if (tmpap.csw & ADIV5_AP_CSW_TRINPROG) {
|
||||
DEBUG_WARN("AP %d: Transaction in progress. AP is not be usable!\n",
|
||||
apsel);
|
||||
DEBUG_WARN("AP %d: Transaction in progress. AP is not be usable!\n", apsel);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* It's valid to so create a heap copy */
|
||||
ap = malloc(sizeof(*ap));
|
||||
if (!ap) { /* malloc failed: heap exhaustion */
|
||||
if (!ap) { /* malloc failed: heap exhaustion */
|
||||
DEBUG_WARN("malloc: failed in %s\n", __func__);
|
||||
return NULL;
|
||||
}
|
||||
|
|
@ -646,10 +632,9 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
|
|||
|
||||
#if defined(ENABLE_DEBUG)
|
||||
uint32_t cfg = adiv5_ap_read(ap, ADIV5_AP_CFG);
|
||||
DEBUG_INFO("AP %3d: IDR=%08"PRIx32" CFG=%08"PRIx32" BASE=%08" PRIx32
|
||||
" CSW=%08"PRIx32, apsel, ap->idr, cfg, ap->base, ap->csw);
|
||||
DEBUG_INFO(" (AHB-AP var%" PRIx32 " rev%" PRIx32 "\n",
|
||||
(ap->idr >> 4) & 0xf, ap->idr >> 28);
|
||||
DEBUG_INFO("AP %3d: IDR=%08" PRIx32 " CFG=%08" PRIx32 " BASE=%08" PRIx32 " CSW=%08" PRIx32, apsel, ap->idr, cfg,
|
||||
ap->base, ap->csw);
|
||||
DEBUG_INFO(" (AHB-AP var%" PRIx32 " rev%" PRIx32 ")\n", (ap->idr >> 4) & 0xf, ap->idr >> 28);
|
||||
#endif
|
||||
adiv5_ap_ref(ap);
|
||||
return ap;
|
||||
|
|
@ -659,7 +644,7 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
|
|||
static void rp_rescue_setup(ADIv5_DP_t *dp)
|
||||
{
|
||||
ADIv5_AP_t *ap = malloc(sizeof(*ap));
|
||||
if (!ap) { /* malloc failed: heap exhaustion */
|
||||
if (!ap) { /* malloc failed: heap exhaustion */
|
||||
DEBUG_WARN("malloc: failed in %s\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
|
@ -673,9 +658,8 @@ static void rp_rescue_setup(ADIv5_DP_t *dp)
|
|||
void adiv5_dp_init(ADIv5_DP_t *dp)
|
||||
{
|
||||
#define DPIDR_PARTNO_MASK 0x0ff00000
|
||||
/* Check IDCODE for a valid designer and sensible PARTNO*/
|
||||
if (((dp->idcode & 0xfff) == 0) ||
|
||||
((dp->idcode & DPIDR_PARTNO_MASK)) == DPIDR_PARTNO_MASK) {
|
||||
/* Check IDCODE for a valid designer and sensible PARTNO */
|
||||
if (((dp->idcode & 0xfff) == 0) || ((dp->idcode & DPIDR_PARTNO_MASK)) == DPIDR_PARTNO_MASK) {
|
||||
DEBUG_WARN("Invalid DP idcode %08" PRIx32 "\n", dp->idcode);
|
||||
free(dp);
|
||||
return;
|
||||
|
|
@ -684,12 +668,10 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
|
|||
rp_rescue_setup(dp);
|
||||
return;
|
||||
}
|
||||
DEBUG_INFO("DPIDR 0x%08" PRIx32 " (v%d %srev%d)\n", dp->idcode,
|
||||
(uint8_t)((dp->idcode >> 12) & 0xf),
|
||||
(dp->idcode & ADIV5_MINDP) ? "MINDP " : "",
|
||||
(uint16_t)(dp->idcode >> 28));
|
||||
DEBUG_INFO("DPIDR 0x%08" PRIx32 " (v%d %srev%d)\n", dp->idcode, (uint8_t)((dp->idcode >> 12) & 0xf),
|
||||
(dp->idcode & ADIV5_MINDP) ? "MINDP " : "", (uint16_t)(dp->idcode >> 28));
|
||||
volatile uint32_t ctrlstat = 0;
|
||||
#if PC_HOSTED == 1
|
||||
#if PC_HOSTED == 1
|
||||
platform_adiv5_dp_defaults(dp);
|
||||
if (!dp->ap_write)
|
||||
dp->ap_write = firmware_ap_write;
|
||||
|
|
@ -718,16 +700,12 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
|
|||
platform_timeout timeout;
|
||||
platform_timeout_set(&timeout, 201);
|
||||
/* Write request for system and debug power up */
|
||||
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT,
|
||||
ctrlstat |= ADIV5_DP_CTRLSTAT_CSYSPWRUPREQ |
|
||||
ADIV5_DP_CTRLSTAT_CDBGPWRUPREQ);
|
||||
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, ctrlstat |= ADIV5_DP_CTRLSTAT_CSYSPWRUPREQ | ADIV5_DP_CTRLSTAT_CDBGPWRUPREQ);
|
||||
/* Wait for acknowledge */
|
||||
while(1) {
|
||||
while (1) {
|
||||
ctrlstat = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT);
|
||||
uint32_t check = ctrlstat & (ADIV5_DP_CTRLSTAT_CSYSPWRUPACK |
|
||||
ADIV5_DP_CTRLSTAT_CDBGPWRUPACK);
|
||||
if (check == (ADIV5_DP_CTRLSTAT_CSYSPWRUPACK |
|
||||
ADIV5_DP_CTRLSTAT_CDBGPWRUPACK))
|
||||
uint32_t check = ctrlstat & (ADIV5_DP_CTRLSTAT_CSYSPWRUPACK | ADIV5_DP_CTRLSTAT_CDBGPWRUPACK);
|
||||
if (check == (ADIV5_DP_CTRLSTAT_CSYSPWRUPACK | ADIV5_DP_CTRLSTAT_CDBGPWRUPACK))
|
||||
break;
|
||||
if (platform_timeout_is_expired(&timeout)) {
|
||||
DEBUG_INFO("DEBUG Power-Up failed\n");
|
||||
|
|
@ -741,14 +719,12 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
|
|||
* so we have a timeout mechanism in addition to the sensing one.
|
||||
*
|
||||
* Write request for debug reset */
|
||||
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT,
|
||||
ctrlstat |= ADIV5_DP_CTRLSTAT_CDBGRSTREQ);
|
||||
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, ctrlstat |= ADIV5_DP_CTRLSTAT_CDBGRSTREQ);
|
||||
|
||||
/* Write request for debug reset release */
|
||||
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT,
|
||||
ctrlstat &= ~ADIV5_DP_CTRLSTAT_CDBGRSTREQ);
|
||||
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, ctrlstat &= ~ADIV5_DP_CTRLSTAT_CDBGRSTREQ);
|
||||
/* Wait for acknowledge */
|
||||
while(1) {
|
||||
while (1) {
|
||||
platform_delay(20);
|
||||
ctrlstat = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT);
|
||||
if (ctrlstat & ADIV5_DP_CTRLSTAT_CDBGRSTACK) {
|
||||
|
|
@ -765,7 +741,7 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
|
|||
uint32_t last_base = 0;
|
||||
int void_aps = 0;
|
||||
dp->refcnt++;
|
||||
for(int i = 0; (i < 256) && (void_aps < 8); i++) {
|
||||
for (int i = 0; (i < 256) && (void_aps < 8); i++) {
|
||||
ADIv5_AP_t *ap = NULL;
|
||||
#if PC_HOSTED == 1
|
||||
if ((!dp->ap_setup) || dp->ap_setup(i))
|
||||
|
|
@ -831,8 +807,7 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
|
|||
adiv5_dp_unref(dp);
|
||||
}
|
||||
|
||||
#define ALIGNOF(x) (((x) & 3) == 0 ? ALIGN_WORD : \
|
||||
(((x) & 1) == 0 ? ALIGN_HALFWORD : ALIGN_BYTE))
|
||||
#define ALIGNOF(x) (((x)&3) == 0 ? ALIGN_WORD : (((x)&1) == 0 ? ALIGN_HALFWORD : ALIGN_BYTE))
|
||||
|
||||
/* Program the CSW and TAR for sequencial access at a given width */
|
||||
static void ap_mem_access_setup(ADIv5_AP_t *ap, uint32_t addr, enum align align)
|
||||
|
|
@ -856,7 +831,7 @@ static void ap_mem_access_setup(ADIv5_AP_t *ap, uint32_t addr, enum align align)
|
|||
}
|
||||
|
||||
/* Extract read data from data lane based on align and src address */
|
||||
void * extract(void *dest, uint32_t src, uint32_t val, enum align align)
|
||||
void *extract(void *dest, uint32_t src, uint32_t val, enum align align)
|
||||
{
|
||||
switch (align) {
|
||||
case ALIGN_BYTE:
|
||||
|
|
@ -893,18 +868,15 @@ void firmware_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len)
|
|||
/* Check for 10 bit address overflow */
|
||||
if ((src ^ osrc) & 0xfffffc00) {
|
||||
osrc = src;
|
||||
adiv5_dp_low_access(ap->dp,
|
||||
ADIV5_LOW_WRITE, ADIV5_AP_TAR, src);
|
||||
adiv5_dp_low_access(ap->dp,
|
||||
ADIV5_LOW_READ, ADIV5_AP_DRW, 0);
|
||||
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src);
|
||||
adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0);
|
||||
}
|
||||
}
|
||||
tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0);
|
||||
extract(dest, src, tmp, align);
|
||||
}
|
||||
|
||||
void firmware_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src,
|
||||
size_t len, enum align align)
|
||||
void firmware_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len, enum align align)
|
||||
{
|
||||
uint32_t odest = dest;
|
||||
|
||||
|
|
@ -915,10 +887,10 @@ void firmware_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src,
|
|||
/* Pack data into correct data lane */
|
||||
switch (align) {
|
||||
case ALIGN_BYTE:
|
||||
tmp = ((uint32_t)*(uint8_t *)src) << ((dest & 3) << 3);
|
||||
tmp = ((uint32_t) * (uint8_t *)src) << ((dest & 3) << 3);
|
||||
break;
|
||||
case ALIGN_HALFWORD:
|
||||
tmp = ((uint32_t)*(uint16_t *)src) << ((dest & 2) << 3);
|
||||
tmp = ((uint32_t) * (uint16_t *)src) << ((dest & 2) << 3);
|
||||
break;
|
||||
case ALIGN_DWORD:
|
||||
case ALIGN_WORD:
|
||||
|
|
@ -932,24 +904,21 @@ void firmware_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src,
|
|||
/* Check for 10 bit address overflow */
|
||||
if ((dest ^ odest) & 0xfffffc00) {
|
||||
odest = dest;
|
||||
adiv5_dp_low_access(ap->dp,
|
||||
ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest);
|
||||
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void firmware_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value)
|
||||
{
|
||||
adiv5_dp_write(ap->dp, ADIV5_DP_SELECT,
|
||||
((uint32_t)ap->apsel << 24)|(addr & 0xF0));
|
||||
adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, ((uint32_t)ap->apsel << 24) | (addr & 0xF0));
|
||||
adiv5_dp_write(ap->dp, addr, value);
|
||||
}
|
||||
|
||||
uint32_t firmware_ap_read(ADIv5_AP_t *ap, uint16_t addr)
|
||||
{
|
||||
uint32_t ret;
|
||||
adiv5_dp_write(ap->dp, ADIV5_DP_SELECT,
|
||||
((uint32_t)ap->apsel << 24)|(addr & 0xF0));
|
||||
adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, ((uint32_t)ap->apsel << 24) | (addr & 0xF0));
|
||||
ret = adiv5_dp_read(ap->dp, addr);
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,78 +23,77 @@
|
|||
|
||||
#include "jtag_scan.h"
|
||||
|
||||
#define ADIV5_APnDP 0x100
|
||||
#define ADIV5_DP_REG(x) (x)
|
||||
#define ADIV5_AP_REG(x) (ADIV5_APnDP | (x))
|
||||
#define ADIV5_APnDP 0x100U
|
||||
#define ADIV5_DP_REG(x) (x)
|
||||
#define ADIV5_AP_REG(x) (ADIV5_APnDP | (x))
|
||||
|
||||
#define ADIV5_DP_BANK0 0x00
|
||||
#define ADIV5_DP_BANK1 0x10
|
||||
#define ADIV5_DP_BANK2 0x20
|
||||
#define ADIV5_DP_BANK3 0x30
|
||||
#define ADIV5_DP_BANK4 0x40
|
||||
#define ADIV5_DP_BANK0 0x00U
|
||||
#define ADIV5_DP_BANK1 0x10U
|
||||
#define ADIV5_DP_BANK2 0x20U
|
||||
#define ADIV5_DP_BANK3 0x30U
|
||||
#define ADIV5_DP_BANK4 0x40U
|
||||
|
||||
/* ADIv5 DP Register addresses */
|
||||
#define ADIV5_DP_IDCODE ADIV5_DP_REG(0x0)
|
||||
#define ADIV5_DP_ABORT ADIV5_DP_REG(0x0)
|
||||
#define ADIV5_DP_CTRLSTAT ADIV5_DP_REG(0x4)
|
||||
#define ADIV5_DP_TARGETID (ADIV5_DP_BANK2 | ADIV5_DP_REG(0x4))
|
||||
#define ADIV5_DP_SELECT ADIV5_DP_REG(0x8)
|
||||
#define ADIV5_DP_RDBUFF ADIV5_DP_REG(0xC)
|
||||
#define ADIV5_DP_TARGETSEL ADIV5_DP_REG(0xC)
|
||||
#define ADIV5_DP_IDCODE ADIV5_DP_REG(0x0U)
|
||||
#define ADIV5_DP_ABORT ADIV5_DP_REG(0x0U)
|
||||
#define ADIV5_DP_CTRLSTAT ADIV5_DP_REG(0x4U)
|
||||
#define ADIV5_DP_TARGETID (ADIV5_DP_BANK2 | ADIV5_DP_REG(0x4U))
|
||||
#define ADIV5_DP_SELECT ADIV5_DP_REG(0x8U)
|
||||
#define ADIV5_DP_RDBUFF ADIV5_DP_REG(0xCU)
|
||||
#define ADIV5_DP_TARGETSEL ADIV5_DP_REG(0xCU)
|
||||
|
||||
#define ADIV5_DP_VERSION_MASK 0xf000
|
||||
#define ADIV5_DPv1 0x1000
|
||||
#define ADIV5_DPv2 0x2000
|
||||
#define ADIV5_MINDP 0x10000
|
||||
#define ADIV5_DP_VERSION_MASK 0xf000U
|
||||
#define ADIV5_DPv1 0x1000U
|
||||
#define ADIV5_DPv2 0x2000U
|
||||
#define ADIV5_MINDP 0x10000U
|
||||
|
||||
/* AP Abort Register (ABORT) */
|
||||
/* Bits 31:5 - Reserved */
|
||||
#define ADIV5_DP_ABORT_ORUNERRCLR (1 << 4)
|
||||
#define ADIV5_DP_ABORT_WDERRCLR (1 << 3)
|
||||
#define ADIV5_DP_ABORT_STKERRCLR (1 << 2)
|
||||
#define ADIV5_DP_ABORT_STKCMPCLR (1 << 1)
|
||||
#define ADIV5_DP_ABORT_ORUNERRCLR (1U << 4U)
|
||||
#define ADIV5_DP_ABORT_WDERRCLR (1U << 3U)
|
||||
#define ADIV5_DP_ABORT_STKERRCLR (1U << 2U)
|
||||
#define ADIV5_DP_ABORT_STKCMPCLR (1U << 1U)
|
||||
/* Bits 5:1 - SW-DP only, reserved in JTAG-DP */
|
||||
#define ADIV5_DP_ABORT_DAPABORT (1 << 0)
|
||||
#define ADIV5_DP_ABORT_DAPABORT (1U << 0U)
|
||||
|
||||
/* Control/Status Register (CTRLSTAT) */
|
||||
#define ADIV5_DP_CTRLSTAT_CSYSPWRUPACK (1u << 31)
|
||||
#define ADIV5_DP_CTRLSTAT_CSYSPWRUPREQ (1u << 30)
|
||||
#define ADIV5_DP_CTRLSTAT_CDBGPWRUPACK (1u << 29)
|
||||
#define ADIV5_DP_CTRLSTAT_CDBGPWRUPREQ (1u << 28)
|
||||
#define ADIV5_DP_CTRLSTAT_CDBGRSTACK (1u << 27)
|
||||
#define ADIV5_DP_CTRLSTAT_CDBGRSTREQ (1u << 26)
|
||||
#define ADIV5_DP_CTRLSTAT_CSYSPWRUPACK (1U << 31U)
|
||||
#define ADIV5_DP_CTRLSTAT_CSYSPWRUPREQ (1U << 30U)
|
||||
#define ADIV5_DP_CTRLSTAT_CDBGPWRUPACK (1U << 29U)
|
||||
#define ADIV5_DP_CTRLSTAT_CDBGPWRUPREQ (1U << 28U)
|
||||
#define ADIV5_DP_CTRLSTAT_CDBGRSTACK (1U << 27U)
|
||||
#define ADIV5_DP_CTRLSTAT_CDBGRSTREQ (1U << 26U)
|
||||
/* Bits 25:24 - Reserved */
|
||||
/* Bits 23:12 - TRNCNT */
|
||||
#define ADIV5_DP_CTRLSTAT_TRNCNT (1u << 12)
|
||||
#define ADIV5_DP_CTRLSTAT_TRNCNT (1U << 12U)
|
||||
/* Bits 11:8 - MASKLANE */
|
||||
#define ADIV5_DP_CTRLSTAT_MASKLANE
|
||||
/* Bits 7:6 - Reserved in JTAG-DP */
|
||||
#define ADIV5_DP_CTRLSTAT_WDATAERR (1u << 7)
|
||||
#define ADIV5_DP_CTRLSTAT_READOK (1u << 6)
|
||||
#define ADIV5_DP_CTRLSTAT_STICKYERR (1u << 5)
|
||||
#define ADIV5_DP_CTRLSTAT_STICKYCMP (1u << 4)
|
||||
#define ADIV5_DP_CTRLSTAT_TRNMODE_MASK (3u << 2)
|
||||
#define ADIV5_DP_CTRLSTAT_STICKYORUN (1u << 1)
|
||||
#define ADIV5_DP_CTRLSTAT_ORUNDETECT (1u << 0)
|
||||
|
||||
#define ADIV5_DP_CTRLSTAT_WDATAERR (1U << 7U)
|
||||
#define ADIV5_DP_CTRLSTAT_READOK (1U << 6U)
|
||||
#define ADIV5_DP_CTRLSTAT_STICKYERR (1U << 5U)
|
||||
#define ADIV5_DP_CTRLSTAT_STICKYCMP (1U << 4U)
|
||||
#define ADIV5_DP_CTRLSTAT_TRNMODE_MASK (3U << 2U)
|
||||
#define ADIV5_DP_CTRLSTAT_STICKYORUN (1U << 1U)
|
||||
#define ADIV5_DP_CTRLSTAT_ORUNDETECT (1U << 0U)
|
||||
|
||||
/* ADIv5 MEM-AP Registers */
|
||||
#define ADIV5_AP_CSW ADIV5_AP_REG(0x00)
|
||||
#define ADIV5_AP_TAR ADIV5_AP_REG(0x04)
|
||||
#define ADIV5_AP_CSW ADIV5_AP_REG(0x00U)
|
||||
#define ADIV5_AP_TAR ADIV5_AP_REG(0x04U)
|
||||
/* 0x08 - Reserved */
|
||||
#define ADIV5_AP_DRW ADIV5_AP_REG(0x0C)
|
||||
#define ADIV5_AP_DB(x) ADIV5_AP_REG(0x10 + (4*(x)))
|
||||
#define ADIV5_AP_DRW ADIV5_AP_REG(0x0CU)
|
||||
#define ADIV5_AP_DB(x) ADIV5_AP_REG(0x10U + (4U * (x)))
|
||||
/* 0x20:0xF0 - Reserved */
|
||||
#define ADIV5_AP_CFG ADIV5_AP_REG(0xF4)
|
||||
#define ADIV5_AP_BASE ADIV5_AP_REG(0xF8)
|
||||
#define ADIV5_AP_IDR ADIV5_AP_REG(0xFC)
|
||||
#define ADIV5_AP_CFG ADIV5_AP_REG(0xF4U)
|
||||
#define ADIV5_AP_BASE ADIV5_AP_REG(0xF8U)
|
||||
#define ADIV5_AP_IDR ADIV5_AP_REG(0xFCU)
|
||||
|
||||
/* Known designers seen in SYSROM-PIDR. Ignore Bit 0 from
|
||||
* the designer bits to get JEDEC Ids with bit 7 ignored.*/
|
||||
#define AP_DESIGNER_FREESCALE 0x00e
|
||||
#define AP_DESIGNER_TEXAS 0x017
|
||||
#define AP_DESIGNER_ATMEL 0x01f
|
||||
#define AP_DESIGNER_STM 0x020
|
||||
#define AP_DESIGNER_FREESCALE 0x00e
|
||||
#define AP_DESIGNER_TEXAS 0x017
|
||||
#define AP_DESIGNER_ATMEL 0x01f
|
||||
#define AP_DESIGNER_STM 0x020
|
||||
/* CPU2 for STM32W(L|B) uses ARM JEDEC continuation (4) and
|
||||
* not STM ARM JEDEC continuation (0) as for CPU1.
|
||||
* See RM0453
|
||||
|
|
@ -103,11 +102,11 @@
|
|||
* vs
|
||||
* 38.13.2 CPU2 ROM1 CoreSight peripheral identity register 4 (C2ROM1_PIDR4)
|
||||
*/
|
||||
#define AP_DESIGNER_STM32WX 0x420
|
||||
#define AP_DESIGNER_CYPRESS 0x034
|
||||
#define AP_DESIGNER_INFINEON 0x041
|
||||
#define AP_DESIGNER_NORDIC 0x244
|
||||
#define AP_DESIGNER_ARM 0x43b
|
||||
#define AP_DESIGNER_STM32WX 0x420
|
||||
#define AP_DESIGNER_CYPRESS 0x034
|
||||
#define AP_DESIGNER_INFINEON 0x041
|
||||
#define AP_DESIGNER_NORDIC 0x244
|
||||
#define AP_DESIGNER_ARM 0x43b
|
||||
/*LPC845 with designer 501. Strange!? */
|
||||
#define AP_DESIGNER_SPECULAR 0x501
|
||||
#define AP_DESIGNER_CS 0x555
|
||||
|
|
@ -116,50 +115,48 @@
|
|||
#define AP_DESIGNER_RASPBERRY 0x927
|
||||
|
||||
/* AP Control and Status Word (CSW) */
|
||||
#define ADIV5_AP_CSW_DBGSWENABLE (1u << 31)
|
||||
#define ADIV5_AP_CSW_DBGSWENABLE (1U << 31U)
|
||||
/* Bits 30:24 - Prot, Implementation defined, for Cortex-M3: */
|
||||
#define ADIV5_AP_CSW_MASTERTYPE_DEBUG (1u << 29)
|
||||
#define ADIV5_AP_CSW_HPROT1 (1u << 25)
|
||||
#define ADIV5_AP_CSW_SPIDEN (1u << 23)
|
||||
#define ADIV5_AP_CSW_MASTERTYPE_DEBUG (1U << 29U)
|
||||
#define ADIV5_AP_CSW_HPROT1 (1U << 25U)
|
||||
#define ADIV5_AP_CSW_SPIDEN (1U << 23U)
|
||||
/* Bits 22:12 - Reserved */
|
||||
/* Bits 11:8 - Mode, must be zero */
|
||||
#define ADIV5_AP_CSW_TRINPROG (1u << 7)
|
||||
#define ADIV5_AP_CSW_DEVICEEN (1u << 6)
|
||||
#define ADIV5_AP_CSW_ADDRINC_NONE (0u << 4)
|
||||
#define ADIV5_AP_CSW_ADDRINC_SINGLE (1u << 4)
|
||||
#define ADIV5_AP_CSW_ADDRINC_PACKED (2u << 4)
|
||||
#define ADIV5_AP_CSW_ADDRINC_MASK (3u << 4)
|
||||
#define ADIV5_AP_CSW_TRINPROG (1U << 7U)
|
||||
#define ADIV5_AP_CSW_DEVICEEN (1U << 6U)
|
||||
#define ADIV5_AP_CSW_ADDRINC_NONE (0U << 4U)
|
||||
#define ADIV5_AP_CSW_ADDRINC_SINGLE (1U << 4U)
|
||||
#define ADIV5_AP_CSW_ADDRINC_PACKED (2U << 4U)
|
||||
#define ADIV5_AP_CSW_ADDRINC_MASK (3U << 4U)
|
||||
/* Bit 3 - Reserved */
|
||||
#define ADIV5_AP_CSW_SIZE_BYTE (0u << 0)
|
||||
#define ADIV5_AP_CSW_SIZE_HALFWORD (1u << 0)
|
||||
#define ADIV5_AP_CSW_SIZE_WORD (2u << 0)
|
||||
#define ADIV5_AP_CSW_SIZE_MASK (7u << 0)
|
||||
#define ADIV5_AP_CSW_SIZE_BYTE (0U << 0U)
|
||||
#define ADIV5_AP_CSW_SIZE_HALFWORD (1U << 0U)
|
||||
#define ADIV5_AP_CSW_SIZE_WORD (2U << 0U)
|
||||
#define ADIV5_AP_CSW_SIZE_MASK (7U << 0U)
|
||||
|
||||
/* AP Debug Base Address Register (BASE) */
|
||||
#define ADIV5_AP_BASE_BASEADDR (0xFFFFF000u)
|
||||
#define ADIV5_AP_BASE_PRESENT (1u << 0)
|
||||
|
||||
#define ADIV5_AP_BASE_BASEADDR (0xFFFFF000U)
|
||||
#define ADIV5_AP_BASE_PRESENT (1U << 0)
|
||||
|
||||
/* ADIv5 Class 0x1 ROM Table Registers */
|
||||
#define ADIV5_ROM_MEMTYPE 0xFCC
|
||||
#define ADIV5_ROM_MEMTYPE_SYSMEM (1u << 0)
|
||||
#define ADIV5_ROM_ROMENTRY_PRESENT (1u << 0)
|
||||
#define ADIV5_ROM_ROMENTRY_OFFSET (0xFFFFF000u)
|
||||
|
||||
#define ADIV5_ROM_MEMTYPE 0xFCCU
|
||||
#define ADIV5_ROM_MEMTYPE_SYSMEM (1U << 0U)
|
||||
#define ADIV5_ROM_ROMENTRY_PRESENT (1U << 0U)
|
||||
#define ADIV5_ROM_ROMENTRY_OFFSET (0xFFFFF000U)
|
||||
|
||||
/* Constants to make RnW parameters more clear in code */
|
||||
#define ADIV5_LOW_WRITE 0
|
||||
#define ADIV5_LOW_READ 1
|
||||
#define ADIV5_LOW_WRITE 0
|
||||
#define ADIV5_LOW_READ 1
|
||||
|
||||
#define SWDP_ACK_OK 0x01
|
||||
#define SWDP_ACK_WAIT 0x02
|
||||
#define SWDP_ACK_FAULT 0x04
|
||||
#define SWDP_ACK_OK 0x01U
|
||||
#define SWDP_ACK_WAIT 0x02U
|
||||
#define SWDP_ACK_FAULT 0x04U
|
||||
|
||||
enum align {
|
||||
ALIGN_BYTE = 0,
|
||||
ALIGN_BYTE = 0,
|
||||
ALIGN_HALFWORD = 1,
|
||||
ALIGN_WORD = 2,
|
||||
ALIGN_DWORD = 3
|
||||
ALIGN_WORD = 2,
|
||||
ALIGN_DWORD = 3
|
||||
};
|
||||
|
||||
typedef struct ADIv5_AP_s ADIv5_AP_t;
|
||||
|
|
@ -169,38 +166,34 @@ typedef struct ADIv5_DP_s {
|
|||
int refcnt;
|
||||
|
||||
uint32_t idcode;
|
||||
uint32_t targetid; /* Contains IDCODE for DPv2 devices.*/
|
||||
uint32_t targetid; /* Contains IDCODE for DPv2 devices.*/
|
||||
|
||||
void (*seq_out)(uint32_t tms_states, size_t clock_cycles);
|
||||
void (*seq_out_parity)(uint32_t tms_states, size_t clock_cycles);
|
||||
uint32_t (*seq_in)(size_t clock_cycles);
|
||||
bool (*seq_in_parity)(uint32_t *ret, size_t clock_cycles);
|
||||
/* dp_low_write returns true if no OK resonse, but ignores errors */
|
||||
bool (*dp_low_write)(struct ADIv5_DP_s *dp, uint16_t addr,
|
||||
const uint32_t data);
|
||||
bool (*dp_low_write)(struct ADIv5_DP_s *dp, uint16_t addr, const uint32_t data);
|
||||
uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint16_t addr);
|
||||
uint32_t (*error)(struct ADIv5_DP_s *dp);
|
||||
uint32_t (*low_access)(struct ADIv5_DP_s *dp, uint8_t RnW,
|
||||
uint16_t addr, uint32_t value);
|
||||
uint32_t (*low_access)(struct ADIv5_DP_s *dp, uint8_t RnW, uint16_t addr, uint32_t value);
|
||||
void (*abort)(struct ADIv5_DP_s *dp, uint32_t abort);
|
||||
|
||||
#if PC_HOSTED == 1
|
||||
bmp_type_t dp_bmp_type;
|
||||
bool (*ap_setup)(int i);
|
||||
void (*ap_cleanup)(int i);
|
||||
void (*ap_regs_read)(ADIv5_AP_t *ap, void *data);
|
||||
uint32_t(*ap_reg_read)(ADIv5_AP_t *ap, int num);
|
||||
void (*ap_reg_write)(ADIv5_AP_t *ap, int num, uint32_t value);
|
||||
void (*ap_regs_read)(ADIv5_AP_t *ap, void *data);
|
||||
uint32_t (*ap_reg_read)(ADIv5_AP_t *ap, int num);
|
||||
void (*ap_reg_write)(ADIv5_AP_t *ap, int num, uint32_t value);
|
||||
void (*read_block)(uint32_t addr, uint8_t *data, int size);
|
||||
void (*dap_write_block_sized)(uint32_t addr, uint8_t *data,
|
||||
int size, enum align align);
|
||||
void (*dap_write_block_sized)(uint32_t addr, uint8_t *data, int size, enum align align);
|
||||
#endif
|
||||
uint32_t (*ap_read)(ADIv5_AP_t *ap, uint16_t addr);
|
||||
void (*ap_write)(ADIv5_AP_t *ap, uint16_t addr, uint32_t value);
|
||||
|
||||
void (*mem_read)(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len);
|
||||
void (*mem_write_sized)(ADIv5_AP_t *ap, uint32_t dest, const void *src,
|
||||
size_t len, enum align align);
|
||||
void (*mem_write_sized)(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len, enum align align);
|
||||
uint8_t dp_jd_index;
|
||||
uint8_t fault;
|
||||
} ADIv5_DP_t;
|
||||
|
|
@ -215,7 +208,7 @@ struct ADIv5_AP_s {
|
|||
uint32_t base;
|
||||
uint32_t csw;
|
||||
uint32_t ap_cortexm_demcr; /* Copy of demcr when starting */
|
||||
uint32_t ap_storage; /* E.g to hold STM32F7 initial DBGMCU_CR value.*/
|
||||
uint32_t ap_storage; /* E.g to hold STM32F7 initial DBGMCU_CR value.*/
|
||||
uint16_t ap_designer;
|
||||
uint16_t ap_partno;
|
||||
};
|
||||
|
|
@ -233,8 +226,7 @@ static inline uint32_t adiv5_dp_error(ADIv5_DP_t *dp)
|
|||
return dp->error(dp);
|
||||
}
|
||||
|
||||
static inline uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t RnW,
|
||||
uint16_t addr, uint32_t value)
|
||||
static inline uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t RnW, uint16_t addr, uint32_t value)
|
||||
{
|
||||
return dp->low_access(dp, RnW, addr, value);
|
||||
}
|
||||
|
|
@ -254,15 +246,12 @@ static inline void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value)
|
|||
return ap->dp->ap_write(ap, addr, value);
|
||||
}
|
||||
|
||||
static inline void adiv5_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src,
|
||||
size_t len)
|
||||
static inline void adiv5_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len)
|
||||
{
|
||||
return ap->dp->mem_read(ap, dest, src, len);
|
||||
}
|
||||
|
||||
static inline void adiv5_mem_write_sized(
|
||||
ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len,
|
||||
enum align align)
|
||||
static inline void adiv5_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len, enum align align)
|
||||
{
|
||||
return ap->dp->mem_write_sized(ap, dest, src, len, align);
|
||||
}
|
||||
|
|
@ -275,14 +264,12 @@ static inline void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value)
|
|||
#else
|
||||
uint32_t adiv5_dp_read(ADIv5_DP_t *dp, uint16_t addr);
|
||||
uint32_t adiv5_dp_error(ADIv5_DP_t *dp);
|
||||
uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t RnW,
|
||||
uint16_t addr, uint32_t value);
|
||||
uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t RnW, uint16_t addr, uint32_t value);
|
||||
void adiv5_dp_abort(struct ADIv5_DP_s *dp, uint32_t abort);
|
||||
uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint16_t addr);
|
||||
void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value);
|
||||
void adiv5_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len);
|
||||
void adiv5_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest,
|
||||
const void *src, size_t len, enum align align);
|
||||
void adiv5_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len, enum align align);
|
||||
void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value);
|
||||
#endif
|
||||
|
||||
|
|
@ -300,18 +287,14 @@ int swdptap_init(ADIv5_DP_t *dp);
|
|||
|
||||
void adiv5_mem_write(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len);
|
||||
uint64_t adiv5_ap_read_pidr(ADIv5_AP_t *ap, uint32_t addr);
|
||||
void * extract(void *dest, uint32_t src, uint32_t val, enum align align);
|
||||
void *extract(void *dest, uint32_t src, uint32_t val, enum align align);
|
||||
|
||||
void firmware_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src,
|
||||
size_t len, enum align align);
|
||||
void firmware_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src,
|
||||
size_t len);
|
||||
void firmware_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len, enum align align);
|
||||
void firmware_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len);
|
||||
void firmware_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value);
|
||||
uint32_t firmware_ap_read(ADIv5_AP_t *ap, uint16_t addr);
|
||||
uint32_t firmware_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW,
|
||||
uint16_t addr, uint32_t value);
|
||||
uint32_t fw_adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t RnW,
|
||||
uint16_t addr, uint32_t value);
|
||||
uint32_t firmware_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, uint16_t addr, uint32_t value);
|
||||
uint32_t fw_adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, uint16_t addr, uint32_t value);
|
||||
uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr);
|
||||
uint32_t fw_adiv5_jtagdp_read(ADIv5_DP_t *dp, uint16_t addr);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue