Merge pull request #310 from UweBonnes/stm32l4r
arget/stm32l4.c: Add stm32l4r series and clean up.
This commit is contained in:
Gareth McMullin
GitHub
commit
d7b173ab39
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@ -25,11 +25,9 @@
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*
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* References:
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* RM0351 STM32L4x5 and STM32L4x6 advanced ARM®-based 32-bit MCUs Rev. 5
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* RM0392 STM32L4x1 advanced ARM®-based 32-bit MCUs Rev. 2
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* RM0393 STM32L4x2 advanced ARM®-based 32-bit MCUs Rev. 2
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* RM0394 STM32L431xx STM32L433xx STM32L443xx advanced ARM®-based 32-bit MCUs
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* Rev.3
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* RM0395 STM32L4x5 advanced ARM®-based 32-bit MCUs Rev.1
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* RM0394 STM32L43xxx STM32L44xxx STM32L45xxx STM32L46xxxx advanced
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* ARM®-based 32-bit MCUs Rev.3
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* RM0432 STM32L4Rxxx and STM32L4Sxxx advanced Arm®-based 32-bit MCU. Rev 1
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*
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*
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*/
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@ -57,9 +55,6 @@ static int stm32l4_flash_erase(struct target_flash *f, target_addr addr, size_t
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static int stm32l4_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len);
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static const char stm32l4_driver_str[] = "STM32L4xx";
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#define PAGE_SIZE 0x800
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/* Flash Program ad Erase Controller Register Map */
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#define FPEC_BASE 0x40022000
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#define FLASH_ACR (FPEC_BASE+0x00)
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@ -107,7 +102,11 @@ static const char stm32l4_driver_str[] = "STM32L4xx";
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#define SR_ERROR_MASK 0xF2
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/* Used in STM32L47*/
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#define OR_DUALBANK (1 << 21)
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/* Used in STM32L47R*/
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#define OR_DB1M (1 << 21)
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#define OR_DBANK (1 << 22)
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#define DBGMCU_IDCODE 0xE0042000
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#define FLASH_SIZE_REG 0x1FFF75E0
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@ -134,69 +133,91 @@ static void stm32l4_add_flash(target *t,
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target_add_flash(t, f);
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}
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static bool stm32l4_attach(target *t);
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enum ID_STM32L4 {
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ID_STM32L43 = 0x435, /* RM0394, Rev.3 */
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ID_STM32L45 = 0x462, /* RM0394, Rev.3 */
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ID_STM32L47 = 0x415, /* RM0351, Rev.5 */
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ID_STM32L49 = 0x461, /* RM0351, Rev.5 */
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ID_STM32L4R = 0x470, /* RM0432, Rev.5 */
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};
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bool stm32l4_probe(target *t)
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{
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uint32_t idcode;
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const char* designator = NULL;
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bool dual_bank = false;
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uint32_t size;
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uint16_t sram1_size = 0;
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uint16_t sram2_size = 0;
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uint16_t sram3_size = 0;
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idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xFFF;
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uint32_t idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xFFF;
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switch(idcode) {
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case 0x461: /* L496/RM0351 */
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case 0x415: /* L471/RM0392, L475/RM0395, L476/RM0351 */
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case 0x462: /* L45x L46x / RM0394 */
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case 0x435: /* L43x L44x / RM0394 */
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t->idcode = idcode;
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t->driver = "STM32L4";
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t->attach = stm32l4_attach;
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target_add_commands(t, stm32l4_cmd_list, "STM32L4");
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return true;
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case ID_STM32L43:
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designator = "STM32L43x";
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sram1_size = 48;
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sram2_size = 16;
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break;
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case ID_STM32L45:
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designator = "STM32L45x";
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sram1_size = 128;
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sram2_size = 32;
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break;
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case ID_STM32L47:
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designator = "STM32L47x";
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sram1_size = 96;
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sram2_size = 32;
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dual_bank = true;
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break;
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case ID_STM32L49:
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designator = "STM32L49x";
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sram1_size = 256;
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sram2_size = 64;
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dual_bank = true;
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break;
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case ID_STM32L4R:
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designator = "STM32L4Rx";
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sram1_size = 192;
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sram2_size = 64;
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sram3_size = 384;
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/* 4 k block in dual bank, 8 k in single bank.*/
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dual_bank = true;
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break;
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default:
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return false;
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}
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}
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static bool stm32l4_attach(target *t)
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{
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uint32_t size = (target_mem_read32(t, FLASH_SIZE_REG) & 0xffff);
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uint32_t bank1_start = 0x08080000; /* default split on 1MiB devices*/
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if (!cortexm_attach(t))
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return false;
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target_mem_map_free(t);
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switch(t->idcode) {
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case 0x461: /* L496/RM0351 */
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case 0x415: /* L471/RM0392, L475/RM0395, L476/RM0351 */
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t->driver = stm32l4_driver_str;
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if (t->idcode == 0x415) {
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target_add_ram(t, 0x10000000, 0x08000);
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target_add_ram(t, 0x20000000, 0x18000);
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} else {
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target_add_ram(t, 0x10000000, 0x10000);
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target_add_ram(t, 0x20000000, 0x40000);
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}
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t->driver = designator;
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target_add_ram(t, 0x10000000, sram2_size << 10);
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/* All L4 beside L47 alias SRAM2 after SRAM1.*/
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uint32_t ramsize = (idcode == ID_STM32L47)?
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sram1_size : (sram1_size + sram2_size + sram3_size);
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target_add_ram(t, 0x20000000, ramsize << 10);
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size = (target_mem_read32(t, FLASH_SIZE_REG) & 0xffff);
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if (dual_bank) {
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uint32_t options = target_mem_read32(t, FLASH_OPTR);
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/* Only 256 and 512 kiB devices evaluate OR_DUALBANK*/
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if ((size < 0x400) && (options & OR_DUALBANK))
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bank1_start = 0x08000000 + (size << 9);
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stm32l4_add_flash(t, 0x08000000, size << 10, PAGE_SIZE, bank1_start);
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return true;
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case 0x462: /* L45x L46x / RM0394 */
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case 0x435: /* L43x L44x / RM0394 */
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t->driver = stm32l4_driver_str;
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if (t->idcode == 0x452) {
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target_add_ram(t, 0x10000000, 0x08000);
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target_add_ram(t, 0x20000000, 0x20000);
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if (idcode == ID_STM32L4R) {
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/* rm0432 Rev. 2 does not mention 1 MB devices or explain DB1M.*/
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if (options & OR_DBANK) {
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stm32l4_add_flash(t, 0x08000000, 0x00100000, 0x1000, 0x08100000);
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stm32l4_add_flash(t, 0x08100000, 0x00100000, 0x1000, 0x08100000);
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} else
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stm32l4_add_flash(t, 0x08000000, 0x00200000, 0x2000, -1);
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} else {
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target_add_ram(t, 0x10000000, 0x04000);
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target_add_ram(t, 0x20000000, 0x0c000);
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if (options & OR_DUALBANK) {
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uint32_t banksize = size << 9;
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stm32l4_add_flash(t, 0x08000000 , banksize, 0x0800, 0x08000000 + banksize);
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stm32l4_add_flash(t, 0x08000000 + banksize, banksize, 0x0800, 0x08000000 + banksize);
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} else {
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uint32_t banksize = size << 10;
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stm32l4_add_flash(t, 0x08000000 , banksize, 0x0800, -1);
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}
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stm32l4_add_flash(t, 0x08000000, size << 10, PAGE_SIZE, bank1_start);
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}
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} else
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stm32l4_add_flash(t, 0x08000000, size << 10, 0x800, -1);
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target_add_commands(t, stm32l4_cmd_list, designator);
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/* Clear all errors in the status register. */
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target_mem_write32(t, FLASH_SR, target_mem_read32(t, FLASH_SR));
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return true;
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}
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return false;
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}
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static void stm32l4_flash_unlock(target *t)
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{
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@ -213,10 +234,17 @@ static int stm32l4_flash_erase(struct target_flash *f, target_addr addr, size_t
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uint16_t sr;
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uint32_t bank1_start = ((struct stm32l4_flash *)f)->bank1_start;
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uint32_t page;
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uint32_t blocksize = f->blocksize;
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stm32l4_flash_unlock(t);
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page = (addr - 0x08000000) / PAGE_SIZE;
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/* Read FLASH_SR to poll for BSY bit */
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while(target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(t))
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return -1;
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/* Fixme: OPTVER always set after reset! Wrong option defaults?*/
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target_mem_write32(t, FLASH_SR, target_mem_read32(t, FLASH_SR));
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page = (addr - 0x08000000) / blocksize;
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while(len) {
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uint32_t cr;
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@ -234,8 +262,8 @@ static int stm32l4_flash_erase(struct target_flash *f, target_addr addr, size_t
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if(target_check_error(t))
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return -1;
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len -= PAGE_SIZE;
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addr += PAGE_SIZE;
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len -= blocksize;
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addr += blocksize;
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page++;
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}
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@ -272,25 +300,18 @@ static int stm32l4_flash_write(struct target_flash *f,
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static bool stm32l4_cmd_erase(target *t, uint32_t action)
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{
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const char spinner[] = "|/-\\";
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int spinindex = 0;
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tc_printf(t, "Erasing flash... This may take a few seconds. ");
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stm32l4_flash_unlock(t);
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/* Erase time is 25 ms. No need for a spinner.*/
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/* Flash erase action start instruction */
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target_mem_write32(t, FLASH_CR, action);
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target_mem_write32(t, FLASH_CR, action | FLASH_CR_STRT);
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/* Read FLASH_SR to poll for BSY bit */
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while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) {
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tc_printf(t, "\b%c", spinner[spinindex++ % 4]);
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if(target_check_error(t)) {
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tc_printf(t, "\n");
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return false;
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}
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}
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tc_printf(t, "\n");
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/* Check for error */
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uint16_t sr = target_mem_read32(t, FLASH_SR);
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@ -320,6 +341,7 @@ static const uint8_t i2offset[9] = {
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static bool stm32l4_option_write(target *t, const uint32_t *values, int len)
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{
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tc_printf(t, "Device will loose connection. Rescan!\n");
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stm32l4_flash_unlock(t);
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target_mem_write32(t, FLASH_OPTKEYR, OPTKEY1);
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target_mem_write32(t, FLASH_OPTKEYR, OPTKEY2);
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@ -332,11 +354,11 @@ static bool stm32l4_option_write(target *t, const uint32_t *values, int len)
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while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(t))
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return true;
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target_mem_write32(t, FLASH_CR, FLASH_CR_LOCK);
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target_mem_write32(t, FLASH_CR, FLASH_CR_OBL_LAUNCH);
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while (target_mem_read32(t, FLASH_CR) & FLASH_CR_OBL_LAUNCH)
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if(target_check_error(t))
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return true;
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target_mem_write32(t, FLASH_CR, FLASH_CR_LOCK);
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return false;
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}
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@ -358,7 +380,7 @@ static bool stm32l4_cmd_option(target *t, int argc, char *argv[])
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{
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uint32_t val;
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uint32_t values[9] = { 0xFFEFF8AA, 0xFFFFFFFF, 0, 0x000000ff,
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0x000000ff, 0xffffffff, 0, 0, 0x000000ff};
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0x000000ff, 0xffffffff, 0, 0xff, 0x000000ff};
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int len;
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bool res = false;
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