stm32f4: Switched to the unified mass erase command and added progress dots to stop GDB timing out
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2f0d35de19
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d82ad89715
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@ -37,24 +37,19 @@
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#include "target_internal.h"
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#include "target_internal.h"
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#include "cortexm.h"
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#include "cortexm.h"
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static bool stm32f4_cmd_erase_mass(target *t, int argc, const char **argv);
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static bool stm32f4_cmd_option(target *t, int argc, char **argv);
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static bool stm32f4_cmd_option(target *t, int argc, char *argv[]);
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static bool stm32f4_cmd_psize(target *t, int argc, char **argv);
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static bool stm32f4_cmd_psize(target *t, int argc, char *argv[]);
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const struct command_s stm32f4_cmd_list[] = {
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const struct command_s stm32f4_cmd_list[] = {
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{"erase_mass", (cmd_handler)stm32f4_cmd_erase_mass,
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"Erase entire flash memory"},
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{"option", (cmd_handler)stm32f4_cmd_option, "Manipulate option bytes"},
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{"option", (cmd_handler)stm32f4_cmd_option, "Manipulate option bytes"},
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{"psize", (cmd_handler)stm32f4_cmd_psize,
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{"psize", (cmd_handler)stm32f4_cmd_psize, "Configure flash write parallelism: (x8|x16|x32(default)|x64)"},
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"Configure flash write parallelism: (x8|x16|x32(default)|x64)"},
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{NULL, NULL, NULL}
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{NULL, NULL, NULL}
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};
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};
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static bool stm32f4_attach(target *t);
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static bool stm32f4_attach(target *t);
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static int stm32f4_flash_erase(struct target_flash *f, target_addr addr,
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static int stm32f4_flash_erase(struct target_flash *f, target_addr addr, size_t len);
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size_t len);
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static int stm32f4_flash_write(struct target_flash *f, target_addr dest, const void *src, size_t len);
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static int stm32f4_flash_write(struct target_flash *f,
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static bool stm32f4_mass_erase(target *t);
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target_addr dest, const void *src, size_t len);
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/* Flash Program ad Erase Controller Register Map */
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/* Flash Program ad Erase Controller Register Map */
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#define FPEC_BASE 0x40023C00
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#define FPEC_BASE 0x40023C00
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@ -146,15 +141,15 @@ static void stm32f4_add_flash(target *t,
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uint32_t addr, size_t length, size_t blocksize,
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uint32_t addr, size_t length, size_t blocksize,
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unsigned int base_sector, int split)
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unsigned int base_sector, int split)
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{
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{
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if (length == 0) return;
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if (length == 0)
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return;
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struct stm32f4_flash *sf = calloc(1, sizeof(*sf));
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struct stm32f4_flash *sf = calloc(1, sizeof(*sf));
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struct target_flash *f;
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if (!sf) { /* calloc failed: heap exhaustion */
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if (!sf) { /* calloc failed: heap exhaustion */
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DEBUG_WARN("calloc: failed in %s\n", __func__);
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DEBUG_WARN("calloc: failed in %s\n", __func__);
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return;
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return;
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}
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}
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f = &sf->f;
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struct target_flash *f = &sf->f;
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f->start = addr;
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f->start = addr;
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f->length = length;
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f->length = length;
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f->blocksize = blocksize;
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f->blocksize = blocksize;
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@ -170,7 +165,7 @@ static void stm32f4_add_flash(target *t,
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static char *stm32f4_get_chip_name(uint32_t idcode)
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static char *stm32f4_get_chip_name(uint32_t idcode)
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{
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{
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switch(idcode){
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switch (idcode) {
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case ID_STM32F40X: /* F40XxE/G */
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case ID_STM32F40X: /* F40XxE/G */
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return "STM32F40x";
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return "STM32F40x";
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case ID_STM32F42X: /* F42XxG/I */
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case ID_STM32F42X: /* F42XxG/I */
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@ -234,6 +229,7 @@ bool stm32f4_probe(target *t)
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case ID_STM32F412: /* F412 RM0402 Rev.4, 256 kB Ram */
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case ID_STM32F412: /* F412 RM0402 Rev.4, 256 kB Ram */
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case ID_STM32F401E: /* F401 D/E RM0368 Rev.3 */
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case ID_STM32F401E: /* F401 D/E RM0368 Rev.3 */
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case ID_STM32F413: /* F413 RM0430 Rev.2, 320 kB Ram, 1.5 MB flash. */
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case ID_STM32F413: /* F413 RM0430 Rev.2, 320 kB Ram, 1.5 MB flash. */
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t->mass_erase = stm32f4_mass_erase;
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t->detach = stm32f4_detach;
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t->detach = stm32f4_detach;
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t->driver = stm32f4_get_chip_name(t->idcode);
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t->driver = stm32f4_get_chip_name(t->idcode);
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t->attach = stm32f4_attach;
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t->attach = stm32f4_attach;
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@ -473,41 +469,30 @@ static int stm32f4_flash_write(struct target_flash *f,
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return 0;
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return 0;
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}
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}
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static bool stm32f4_cmd_erase_mass(target *t, int argc, const char **argv)
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static bool stm32f4_mass_erase(target *t)
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{
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{
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(void)argc;
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struct stm32f4_flash *sf = (struct stm32f4_flash *)t->flash;
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(void)argv;
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const char spinner[] = "|/-\\";
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int spinindex = 0;
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struct target_flash *f = t->flash;
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struct stm32f4_flash *sf = (struct stm32f4_flash *)f;
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tc_printf(t, "Erasing flash... This may take a few seconds. ");
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stm32f4_flash_unlock(t);
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stm32f4_flash_unlock(t);
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/* Flash mass erase start instruction */
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/* Flash mass erase start instruction */
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uint32_t cr = FLASH_CR_MER;
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uint32_t ctrl_reg = FLASH_CR_MER;
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if (sf->bank_split)
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if (sf->bank_split)
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cr |= FLASH_CR_MER1;
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ctrl_reg |= FLASH_CR_MER1;
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target_mem_write32(t, FLASH_CR, cr);
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target_mem_write32(t, FLASH_CR, ctrl_reg);
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target_mem_write32(t, FLASH_CR, cr | FLASH_CR_STRT);
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target_mem_write32(t, FLASH_CR, ctrl_reg | FLASH_CR_STRT);
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platform_timeout timeout;
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platform_timeout_set(&timeout, 500);
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/* Read FLASH_SR to poll for BSY bit */
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/* Read FLASH_SR to poll for BSY bit */
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while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) {
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while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) {
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tc_printf(t, "\b%c", spinner[spinindex++ % 4]);
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if (target_check_error(t))
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if(target_check_error(t)) {
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tc_printf(t, "\n");
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return false;
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return false;
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target_print_progress(&timeout);
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}
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}
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}
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tc_printf(t, "\n");
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/* Check for error */
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/* Check for error */
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uint32_t sr = target_mem_read32(t, FLASH_SR);
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const uint32_t result = target_mem_read32(t, FLASH_SR);
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if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP))
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return !(result & SR_ERROR_MASK) && (result & SR_EOP);
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return false;
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return true;
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}
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}
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/* Dev | DOC |Rev|ID |OPTCR |OPTCR |OPTCR1 |OPTCR1 | OPTCR2
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/* Dev | DOC |Rev|ID |OPTCR |OPTCR |OPTCR1 |OPTCR1 | OPTCR2
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