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Disable ADIv5 timeout while target is running.

This commit is contained in:
Gareth McMullin 2013-06-19 21:05:53 +12:00
parent d90e10cdba
commit d8f737fc53
4 changed files with 13 additions and 3 deletions
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6
src/adiv5_jtagdp.c
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@ -92,10 +92,14 @@ static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t R
jtag_dev_write_ir(dp->dev, APnDP?IR_APACC:IR_DPACC); jtag_dev_write_ir(dp->dev, APnDP?IR_APACC:IR_DPACC);
int tries = 1000;
do { do {
jtag_dev_shift_dr(dp->dev, (uint8_t*)&response, (uint8_t*)&request, 35); jtag_dev_shift_dr(dp->dev, (uint8_t*)&response, (uint8_t*)&request, 35);
ack = response & 0x07; ack = response & 0x07;
} while(ack == JTAGDP_ACK_WAIT); } while(--tries && (ack == JTAGDP_ACK_WAIT));
if (dp->allow_timeout && (ack == JTAGDP_ACK_WAIT))
return 0;
if((ack != JTAGDP_ACK_OK)) { if((ack != JTAGDP_ACK_OK)) {
/* Fatal error if invalid ACK response */ /* Fatal error if invalid ACK response */

4
src/adiv5_swdp.c
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@ -135,8 +135,8 @@ static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW
ack = swdptap_seq_in(3); ack = swdptap_seq_in(3);
} while(--tries && ack == SWDP_ACK_WAIT); } while(--tries && ack == SWDP_ACK_WAIT);
if(!tries) if (dp->allow_timeout && (ack == SWDP_ACK_WAIT))
PLATFORM_FATAL_ERROR(1); return 0;
if(ack == SWDP_ACK_FAULT) { if(ack == SWDP_ACK_FAULT) {
dp->fault = 1; dp->fault = 1;

4
src/cortexm.c
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@ -584,6 +584,7 @@ cortexm_halt_request(struct target_s *target)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(target); ADIv5_AP_t *ap = adiv5_target_ap(target);
ap->dp->allow_timeout = false;
adiv5_ap_mem_write(ap, CORTEXM_DHCSR, adiv5_ap_mem_write(ap, CORTEXM_DHCSR,
CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_HALT | CORTEXM_DHCSR_C_DEBUGEN); CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_HALT | CORTEXM_DHCSR_C_DEBUGEN);
} }
@ -596,6 +597,8 @@ cortexm_halt_wait(struct target_s *target)
if (!(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_HALT)) if (!(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_HALT))
return 0; return 0;
ap->dp->allow_timeout = false;
/* We've halted. Let's find out why. */ /* We've halted. Let's find out why. */
uint32_t dfsr = adiv5_ap_mem_read(ap, CORTEXM_DFSR); uint32_t dfsr = adiv5_ap_mem_read(ap, CORTEXM_DFSR);
adiv5_ap_mem_write(ap, CORTEXM_DFSR, dfsr); /* write back to reset */ adiv5_ap_mem_write(ap, CORTEXM_DFSR, dfsr); /* write back to reset */
@ -654,6 +657,7 @@ cortexm_halt_resume(struct target_s *target, bool step)
} }
adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr); adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr);
ap->dp->allow_timeout = true;
} }
static int cortexm_fault_unwind(struct target_s *target) static int cortexm_fault_unwind(struct target_s *target)

2
src/include/adiv5.h
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@ -106,6 +106,8 @@ typedef struct ADIv5_DP_s {
uint32_t idcode; uint32_t idcode;
bool allow_timeout;
void (*dp_write)(struct ADIv5_DP_s *dp, uint8_t addr, uint32_t value); void (*dp_write)(struct ADIv5_DP_s *dp, uint8_t addr, uint32_t value);
uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint8_t addr); uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint8_t addr);