Added support for STM32F0.
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1ce2af4819
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@ -8,7 +8,8 @@ _start:
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ldr r3, _size
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mov r5, #1
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_next:
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cbz r3, _done
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cmp r3, #0
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beq _done
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@ Write PG command to FLASH_CR
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str r5, [r0, #0x10]
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@ Write data to flash (half-word)
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@ -58,6 +58,7 @@ static int stm32f1_flash_write(struct target_s *target, uint32_t dest,
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static const char stm32f1_driver_str[] = "STM32, Medium density.";
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static const char stm32hd_driver_str[] = "STM32, High density.";
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static const char stm32f3_driver_str[] = "STM32F3xx";
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static const char stm32f0_driver_str[] = "STM32F0xx";
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static const char stm32f1_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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/* "<!DOCTYPE memory-map "
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@ -111,6 +112,7 @@ static const char stm32hd_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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#define SR_EOP 0x20
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#define DBGMCU_IDCODE 0xE0042000
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#define DBGMCU_IDCODE_F0 0x40015800
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uint16_t stm32f1_flash_write_stub[] = {
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// _start:
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@ -121,7 +123,8 @@ uint16_t stm32f1_flash_write_stub[] = {
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0x4b09, // ldr r3, [pc, #36] // _size
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0x2501, // movs r5, #1
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// _next:
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0xb153, // cbz r3, _done
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0x2b00, // cmp r3, #0
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0xd00a, // beq _done
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0x6105, // str r5, [r0, #16]
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0x8814, // ldrh r4, [r2]
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0x800c, // strh r4, [r1]
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@ -134,10 +137,9 @@ uint16_t stm32f1_flash_write_stub[] = {
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0x3b02, // subs r3, #2
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0x3102, // adds r1, #2
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0x3202, // adds r2, #2
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0xe7f3, // b _next
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0xe7f2, // b _next
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// _done:
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0xbe00, // bkpt
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0x0000,
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// .org 0x28
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// _flashbase:
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0x2000, 0x4002, // .word 0x40022000 (FPEC_BASE)
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@ -180,9 +182,20 @@ int stm32f1_probe(struct target_s *target)
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target->flash_write = stm32f1_flash_write;
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target_add_commands(target, stm32f1_cmd_list, "STM32");
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return 0;
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default:
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return -1;
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}
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}
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idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE_F0);
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switch(idcode & 0xFFF) {
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case 0x440: /* STM32F0 */
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target->driver = stm32f0_driver_str;
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target->xml_mem_map = stm32f1_xml_memory_map;
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target->flash_erase = stm32md_flash_erase;
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target->flash_write = stm32f1_flash_write;
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target_add_commands(target, stm32f1_cmd_list, "STM32");
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return 0;
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}
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return -1;
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}
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static void stm32f1_flash_unlock(ADIv5_AP_t *ap)
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