Merge pull request #276 from gsmcmullin/cortexa-remove-ahb
cortexa: Remove problematic code for AHB access.
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commit
eaaa7d2cc2
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@ -60,7 +60,6 @@ static uint32_t read_gpreg(target *t, uint8_t regno);
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struct cortexa_priv {
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uint32_t base;
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ADIv5_AP_t *apb;
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ADIv5_AP_t *ahb;
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struct {
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uint32_t r[16];
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uint32_t cpsr;
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@ -217,19 +216,6 @@ static uint32_t va_to_pa(target *t, uint32_t va)
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return pa;
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}
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static void cortexa_mem_read(target *t, void *dest, target_addr src, size_t len)
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{
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/* Clean cache before reading */
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for (uint32_t cl = src & ~(CACHE_LINE_LENGTH-1);
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cl < src + len; cl += CACHE_LINE_LENGTH) {
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write_gpreg(t, 0, cl);
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apb_write(t, DBGITR, MCR | DCCMVAC);
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}
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ADIv5_AP_t *ahb = ((struct cortexa_priv*)t->priv)->ahb;
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adiv5_mem_read(ahb, dest, va_to_pa(t, src), len);
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}
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static void cortexa_slow_mem_read(target *t, void *dest, target_addr src, size_t len)
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{
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struct cortexa_priv *priv = t->priv;
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@ -269,18 +255,6 @@ static void cortexa_slow_mem_read(target *t, void *dest, target_addr src, size_t
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}
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}
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static void cortexa_mem_write(target *t, target_addr dest, const void *src, size_t len)
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{
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/* Clean and invalidate cache before writing */
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for (uint32_t cl = dest & ~(CACHE_LINE_LENGTH-1);
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cl < dest + len; cl += CACHE_LINE_LENGTH) {
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write_gpreg(t, 0, cl);
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apb_write(t, DBGITR, MCR | DCCIMVAC);
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}
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ADIv5_AP_t *ahb = ((struct cortexa_priv*)t->priv)->ahb;
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adiv5_mem_write(ahb, va_to_pa(t, dest), src, len);
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}
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static void cortexa_slow_mem_write_bytes(target *t, target_addr dest, const uint8_t *src, size_t len)
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{
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struct cortexa_priv *priv = t->priv;
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@ -338,8 +312,7 @@ static void cortexa_slow_mem_write(target *t, target_addr dest, const void *src,
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static bool cortexa_check_error(target *t)
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{
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struct cortexa_priv *priv = t->priv;
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ADIv5_AP_t *ahb = priv->ahb;
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bool err = (ahb && (adiv5_dp_error(ahb->dp)) != 0) || priv->mmu_fault;
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bool err = priv->mmu_fault;
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priv->mmu_fault = false;
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return err;
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}
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@ -355,25 +328,8 @@ bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base)
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t->priv = priv;
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t->priv_free = free;
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priv->apb = apb;
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/* FIXME Find a better way to find the AHB. This is likely to be
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* device specific. */
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priv->ahb = adiv5_new_ap(apb->dp, 0);
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adiv5_ap_ref(priv->ahb);
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if (false) {
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/* FIXME: This used to be if ((priv->ahb->idr & 0xfffe00f) == 0x4770001)
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* Accessing memory directly through the AHB is much faster, but can
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* result in data inconsistencies if the L2 cache is enabled.
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*/
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/* This is an AHB */
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t->mem_read = cortexa_mem_read;
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t->mem_write = cortexa_mem_write;
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} else {
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/* This is not an AHB, fall back to slow APB access */
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adiv5_ap_unref(priv->ahb);
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priv->ahb = NULL;
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t->mem_read = cortexa_slow_mem_read;
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t->mem_write = cortexa_slow_mem_write;
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}
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t->mem_read = cortexa_slow_mem_read;
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t->mem_write = cortexa_slow_mem_write;
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priv->base = debug_base;
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/* Set up APB CSW, we won't touch this again */
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