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cortexa: Wait for instruction complete on resume, and timeout if no response.

This commit is contained in:
Gareth McMullin 2016-10-25 10:03:56 -07:00
parent 917c107ded
commit f40883f2b2
1 changed files with 23 additions and 4 deletions
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27
src/target/cortexa.c
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@ -449,7 +449,16 @@ void cortexa_detach(target *t)
/* Invalidate cache */
apb_write(t, DBGITR, MCR | ICIALLU);
uint32_t dbgdscr = apb_read(t, DBGDSCR);
platform_timeout to;
platform_timeout_set(&to, 200);
/* Wait for instruction to complete */
uint32_t dbgdscr;
do {
dbgdscr = apb_read(t, DBGDSCR);
} while (!(dbgdscr & DBGDSCR_INSTRCOMPL) &&
!platform_timeout_is_expired(&to));
/* Disable halting debug mode */
dbgdscr &= ~(DBGDSCR_HDBGEN | DBGDSCR_ITREN);
apb_write(t, DBGDSCR, dbgdscr);
@ -648,8 +657,17 @@ void cortexa_halt_resume(target *t, bool step)
apb_write(t, DBGITR, MCR | ICIALLU); /* invalidate cache */
/* Disable DBGITR. Not sure why, but RRQ is ignored otherwise. */
uint32_t dbgdscr = apb_read(t, DBGDSCR);
platform_timeout to;
platform_timeout_set(&to, 200);
/* Wait for instruction to complete */
uint32_t dbgdscr;
do {
dbgdscr = apb_read(t, DBGDSCR);
} while (!(dbgdscr & DBGDSCR_INSTRCOMPL) &&
!platform_timeout_is_expired(&to));
/* Disable DBGITR. Not sure why, but RRQ is ignored otherwise. */
if (step)
dbgdscr |= DBGDSCR_INTDIS;
else
@ -661,7 +679,8 @@ void cortexa_halt_resume(target *t, bool step)
apb_write(t, DBGDRCR, DBGDRCR_CSE | DBGDRCR_RRQ);
dbgdscr = apb_read(t, DBGDSCR);
DEBUG("%s: DBGDSCR = 0x%08"PRIx32"\n", __func__, dbgdscr);
} while (!(dbgdscr & DBGDSCR_RESTARTED));
} while (!(dbgdscr & DBGDSCR_RESTARTED) &&
!platform_timeout_is_expired(&to));
}
/* Breakpoints */