target/adi: rework handling of TARGETID
add missing fetching of targetid in jlink probes clarify how targetid is being read handle idcode as debug_port_id use targetid when available to identify device in probe routine
This commit is contained in:
Rafael Silva
Rachel Mant
parent
ad65f4a7c7
commit
f435bd2136
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@ -180,12 +180,22 @@ int jlink_swdp_scan(bmp_info_t *info)
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free(dp);
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return 0;
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}
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dp->version = (dp->debug_port_id & ADIV5_DP_DPIDR_VERSION_MASK) >> ADIV5_DP_DPIDR_VERSION_OFFSET;
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dp->dp_read = jlink_adiv5_swdp_read;
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dp->error = jlink_adiv5_swdp_error;
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dp->low_access = jlink_adiv5_swdp_low_access;
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dp->abort = jlink_adiv5_swdp_abort;
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jlink_adiv5_swdp_error(dp);
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if (dp->version >= 2) {
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/* READ TARGETID, only available on DPv2 or later */
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adiv5_dp_write(dp, ADIV5_DP_SELECT, 2); /* TARGETID is on bank 2 */
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dp->target_id = adiv5_dp_read(dp, ADIV5_DP_TARGETID);
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adiv5_dp_write(dp, ADIV5_DP_SELECT, 0);
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}
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adiv5_dp_init(dp);
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return target_list?1:0;
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}
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@ -1078,17 +1078,20 @@ int stlink_enter_debug_swd(bmp_info_t *info, ADIv5_DP_t *dp)
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if (stlink_usb_error_check(data, true))
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exit( -1);
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dp->debug_port_id = stlink_read_coreid();
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dp->version = (dp->debug_port_id & ADIV5_DP_DPIDR_VERSION_MASK) >> ADIV5_DP_DPIDR_VERSION_OFFSET;
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dp->dp_read = stlink_dp_read;
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dp->error = stlink_dp_error;
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dp->low_access = stlink_dp_low_access;
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dp->abort = stlink_dp_abort;
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stlink_dp_error(dp);
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if ((dp->debug_port_id & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) {
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adiv5_dp_write(dp, ADIV5_DP_SELECT, 2);
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dp->targetid = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT);
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if (dp->version >= 2) {
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/* READ TARGETID, only available on DPv2 or later */
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adiv5_dp_write(dp, ADIV5_DP_SELECT, 2); /* TARGETID is on bank 2 */
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dp->target_id = adiv5_dp_read(dp, ADIV5_DP_TARGETID);
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adiv5_dp_write(dp, ADIV5_DP_SELECT, 0);
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DEBUG_INFO("TARGETID 0x%08" PRIx32 "\n", dp->targetid);
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}
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return 0;
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}
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@ -332,7 +332,7 @@ static uint32_t cortexm_initial_halt(ADIv5_AP_t *ap)
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const uint32_t dhcsr_ctl = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN | CORTEXM_DHCSR_C_HALT;
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const uint32_t dhcsr_valid = CORTEXM_DHCSR_S_HALT | CORTEXM_DHCSR_C_DEBUGEN;
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const bool use_low_access = !(ap->dp->debug_port_id & ADIV5_DP_DPIDR_MINDP);
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const bool use_low_access = !ap->dp->mindp;
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platform_timeout halt_timeout;
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platform_timeout_set(&halt_timeout, cortexm_wait_timeout);
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@ -682,30 +682,44 @@ static void rp_rescue_setup(ADIv5_DP_t *dp)
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void adiv5_dp_init(ADIv5_DP_t *dp)
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{
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/* designer code is in the same format in IDCODE and DPIDR */
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/* common handling */
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/*
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* the code in the DPIDR is in the form
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* the code in the DPIDR/IDCODE is in the form
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* Bits 10:7 - JEP-106 Continuation code
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* Bits 6:0 - JEP-106 Identity code
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* here we convert it to our internal representation, See JEP-106 code list
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* note, this is the code of the designer not the implementer, we expect it to be ARM
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*/
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const uint16_t designer = (dp->debug_port_id & ADIV5_DP_DPIDR_DESIGNER_MASK) >> ADIV5_DP_DPIDR_DESIGNER_OFFSET;
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dp->designer_code = (designer & ADIV5_DP_DESIGNER_JEP106_CONT_MASK) << 1U |
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(designer & ADIV5_DP_DESIGNER_JEP106_CODE_MASK);
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dp->partno = (dp->debug_port_id & ADIV5_DP_DPIDR_PARTNO_MASK) >> ADIV5_DP_DPIDR_PARTNO_OFFSET;
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dp->designer_code =
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(designer & ADIV5_DP_DESIGNER_JEP106_CONT_MASK) << 1U | (designer & ADIV5_DP_DESIGNER_JEP106_CODE_MASK);
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/* Check DPIDR for a valid manufacturer and sensible PARTNO */
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if (dp->designer_code == 0 || dp->partno == 0xff7fU) {
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DEBUG_WARN("Invalid DP DPIDR %08" PRIx32 "\n", dp->debug_port_id);
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/* on JTAG IDCODE this is actually the version */
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dp->revision = (dp->debug_port_id & ADIV5_DP_DPIDR_REVISION_MASK) >> ADIV5_DP_DPIDR_REVISION_OFFSET;
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if (dp->version > 0) {
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/* debug_port_id is valid DPIDR */
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dp->partno = (dp->debug_port_id & ADIV5_DP_DPIDR_PARTNO_MASK) >> ADIV5_DP_DPIDR_PARTNO_OFFSET;
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dp->mindp = !!(dp->debug_port_id & ADIV5_DP_DPIDR_MINDP);
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} else {
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/* called from JTAG scan, debug_port_id is JTAG TAP IDCODE */
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dp->partno = (dp->debug_port_id & JTAG_IDCODE_PARTNO_MASK) >> JTAG_IDCODE_PARTNO_OFFSET;
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dp->mindp = false;
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}
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/* Check for a valid designer */
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if (dp->designer_code == 0) {
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DEBUG_WARN("Invalid DP ID %08" PRIx32 "\n", dp->debug_port_id);
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free(dp);
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return;
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}
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DEBUG_INFO("DPIDR 0x%08" PRIx32 " (v%d %srev%d) designer 0x%" PRIx32 " partno 0x%" PRIx32 "\n", dp->debug_port_id,
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(uint8_t)((dp->debug_port_id & ADIV5_DP_DPIDR_VERSION_MASK) >> ADIV5_DP_DPIDR_VERSION_OFFSET),
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(dp->debug_port_id & ADIV5_DP_DPIDR_MINDP) ? "MINDP " : "",
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(uint8_t)((dp->debug_port_id & ADIV5_DP_DPIDR_REVISION_MASK) >> ADIV5_DP_DPIDR_REVISION_OFFSET), dp->designer_code,
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dp->partno);
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DEBUG_INFO("DP ID 0x%08" PRIx32 " (v%d %srev%d) designer 0x%" PRIx32 " partno 0x%" PRIx32 "\n", dp->debug_port_id,
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dp->version, dp->mindp ? "MINDP " : "", dp->revision, dp->designer_code, dp->partno);
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if (dp->version >= 2 && dp->target_id != 0)
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DEBUG_INFO("TARGETID 0x%08" PRIx32 "\n", dp->target_id);
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if (dp->designer_code == JEP106_MANUFACTURER_RASPBERRY && dp->partno == 0x2) {
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rp_rescue_setup(dp);
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@ -41,7 +41,7 @@
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#define ADIV5_DP_DPIDR ADIV5_DP_REG(0x0U)
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#define ADIV5_DP_ABORT ADIV5_DP_REG(0x0U)
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#define ADIV5_DP_CTRLSTAT ADIV5_DP_REG(0x4U)
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#define ADIV5_DP_TARGETID (ADIV5_DP_BANK2 | ADIV5_DP_REG(0x4U))
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#define ADIV5_DP_TARGETID ADIV5_DP_REG(0x4U) /* ADIV5_DP_BANK2 */
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#define ADIV5_DP_SELECT ADIV5_DP_REG(0x8U)
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#define ADIV5_DP_RDBUFF ADIV5_DP_REG(0xCU)
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#define ADIV5_DP_TARGETSEL ADIV5_DP_REG(0xCU)
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@ -68,7 +68,7 @@
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#define ADIV5_DP_TARGETID_TDESIGNER_OFFSET 1U
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#define ADIV5_DP_TARGETID_TDESIGNER_MASK (0x7ffU << ADIV5_DP_TARGETID_TDESIGNER_OFFSET)
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/* DP DPIDR/TARGETID DESIGNER */
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/* DP DPIDR/TARGETID/IDCODE DESIGNER */
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/* Bits 10:7 - JEP-106 Continuation code */
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/* Bits 6:0 - JEP-106 Identity code */
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#define ADIV5_DP_DESIGNER_JEP106_CONT_OFFSET 7U
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@ -146,6 +146,14 @@
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#define ADIV5_ROM_ROMENTRY_PRESENT (1U << 0U)
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#define ADIV5_ROM_ROMENTRY_OFFSET (0xFFFFF000U)
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/* JTAG TAP IDCODE */
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#define JTAG_IDCODE_VERSION_OFFSET 28U
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#define JTAG_IDCODE_VERSION_MASK (0xfU << JTAG_IDCODE_VERSION_OFFSET)
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#define JTAG_IDCODE_PARTNO_OFFSET 12U
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#define JTAG_IDCODE_PARTNO_MASK (0xffffU << JTAG_IDCODE_PARTNO_OFFSET)
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#define JTAG_IDCODE_DESIGNER_OFFSET 1U
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#define JTAG_IDCODE_DESIGNER_MASK (0x7ffU << JTAG_IDCODE_DESIGNER_OFFSET)
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/* Constants to make RnW parameters more clear in code */
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#define ADIV5_LOW_WRITE 0
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#define ADIV5_LOW_READ 1
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@ -220,11 +228,7 @@ typedef struct ADIv5_DP_s {
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int refcnt;
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uint32_t debug_port_id;
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uint16_t designer_code;
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uint16_t partno;
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uint32_t targetid; /* Contains IDCODE for DPv2 devices.*/
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uint32_t target_id; /* present on DPv2 or later */
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void (*seq_out)(uint32_t tms_states, size_t clock_cycles);
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void (*seq_out_parity)(uint32_t tms_states, size_t clock_cycles);
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@ -254,6 +258,15 @@ typedef struct ADIv5_DP_s {
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void (*mem_write_sized)(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len, enum align align);
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uint8_t dp_jd_index;
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uint8_t fault;
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uint8_t version;
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uint8_t revision;
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bool mindp;
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/* DP designer (not implementer!) and partno */
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uint16_t designer_code;
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uint16_t partno;
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} ADIv5_DP_t;
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struct ADIv5_AP_s {
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@ -48,11 +48,7 @@ void adiv5_jtag_dp_handler(uint8_t jd_index)
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}
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dp->dp_jd_index = jd_index;
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/* From the ADI spec :
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* The architecture does not require that the TAP IDCODE
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* register value and the DPIDR (ADIv5) value are the same
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* should read DPIDR here
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*/
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/* JTAG routine passes IDCODE to port ID and version = 0 */
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dp->debug_port_id = jtag_devs[jd_index].jd_idcode;
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if ((PC_HOSTED == 0 ) || (!platform_jtag_dp_init(dp))) {
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dp->dp_read = fw_adiv5_jtagdp_read;
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@ -93,8 +93,6 @@ int adiv5_swdp_scan(uint32_t targetid)
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* 0x1a Arm CoreSight SW-DP activation sequence
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* 20 bits start of reset another reset sequence*/
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initial_dp->seq_out(0x1a0, 12);
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uint32_t dpidr = 0;
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volatile uint32_t target_id = 0;
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bool scan_multidrop = true;
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if (!targetid || !initial_dp->dp_low_write) {
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/* No targetID given on the command line or probe can not
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@ -102,7 +100,7 @@ int adiv5_swdp_scan(uint32_t targetid)
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dp_line_reset(initial_dp);
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TRY_CATCH (e, EXCEPTION_ALL) {
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dpidr = initial_dp->dp_read(initial_dp, ADIV5_DP_DPIDR);
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initial_dp->debug_port_id = initial_dp->dp_read(initial_dp, ADIV5_DP_DPIDR);
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}
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if (e.type || initial_dp->fault) {
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scan_multidrop = false;
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@ -114,24 +112,27 @@ int adiv5_swdp_scan(uint32_t targetid)
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initial_dp->fault = 0;
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TRY_CATCH (e, EXCEPTION_ALL) {
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dpidr = initial_dp->dp_read(initial_dp, ADIV5_DP_DPIDR);
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initial_dp->debug_port_id = initial_dp->dp_read(initial_dp, ADIV5_DP_DPIDR);
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}
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if (e.type || initial_dp->fault) {
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DEBUG_WARN("No usable DP found\n");
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return -1;
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}
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}
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if ((dpidr & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) {
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initial_dp->version =
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(initial_dp->debug_port_id & ADIV5_DP_DPIDR_VERSION_MASK) >> ADIV5_DP_DPIDR_VERSION_OFFSET;
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if (initial_dp->version >= 2) {
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scan_multidrop = true;
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/* Read TargetID. Can be done with device in WFI, sleep or reset!*/
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adiv5_dp_write(initial_dp, ADIV5_DP_SELECT, 2);
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target_id = adiv5_dp_read(initial_dp, ADIV5_DP_CTRLSTAT);
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adiv5_dp_write(initial_dp, ADIV5_DP_SELECT, 2); /* TARGETID is on bank 2 */
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initial_dp->target_id = adiv5_dp_read(initial_dp, ADIV5_DP_TARGETID);
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adiv5_dp_write(initial_dp, ADIV5_DP_SELECT, 0);
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DEBUG_INFO("TARGETID %08" PRIx32 "\n", target_id);
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const uint16_t tdesigner =
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(target_id & ADIV5_DP_TARGETID_TDESIGNER_MASK) >> ADIV5_DP_TARGETID_TDESIGNER_OFFSET;
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const uint16_t tpartno = (target_id & ADIV5_DP_TARGETID_TPARTNO_MASK) >> ADIV5_DP_TARGETID_TPARTNO_OFFSET;
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(initial_dp->target_id & ADIV5_DP_TARGETID_TDESIGNER_MASK) >> ADIV5_DP_TARGETID_TDESIGNER_OFFSET;
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const uint16_t tpartno =
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(initial_dp->target_id & ADIV5_DP_TARGETID_TPARTNO_MASK) >> ADIV5_DP_TARGETID_TPARTNO_OFFSET;
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/* convert it to our internal representation, See JEP-106 code list */
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const uint16_t designer_code = (tdesigner & ADIV5_DP_DESIGNER_JEP106_CONT_MASK) << 1U |
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(tdesigner & ADIV5_DP_DESIGNER_JEP106_CODE_MASK);
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@ -150,23 +151,25 @@ int adiv5_swdp_scan(uint32_t targetid)
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scan_multidrop = false;
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}
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} else {
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target_id = targetid;
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initial_dp->target_id = targetid;
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}
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const volatile size_t nr_dps = (scan_multidrop) ? 16U : 1U;
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volatile uint32_t dp_targetid;
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volatile uint32_t dp_debug_port_id;
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for (volatile size_t i = 0; i < nr_dps; i++) {
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if (scan_multidrop) {
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dp_line_reset(initial_dp);
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dp_targetid = (i << 28U) | (target_id & 0x0fffffffU);
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dp_targetid = (i << 28U) | (initial_dp->target_id & 0x0fffffffU);
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initial_dp->dp_low_write(initial_dp, ADIV5_DP_TARGETSEL, dp_targetid);
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TRY_CATCH (e, EXCEPTION_ALL) {
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dpidr = initial_dp->dp_read(initial_dp, ADIV5_DP_DPIDR);
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dp_debug_port_id = initial_dp->dp_read(initial_dp, ADIV5_DP_DPIDR);
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}
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if (e.type || initial_dp->fault) {
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continue;
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}
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} else {
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dp_targetid = target_id;
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dp_debug_port_id = initial_dp->debug_port_id;
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dp_targetid = initial_dp->target_id;
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}
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ADIv5_DP_t *dp = calloc(1, sizeof(*dp));
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if (!dp) { /* calloc failed: heap exhaustion */
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@ -174,8 +177,9 @@ int adiv5_swdp_scan(uint32_t targetid)
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continue;
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}
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memcpy(dp, initial_dp, sizeof(ADIv5_DP_t));
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dp->debug_port_id = dpidr;
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dp->targetid = dp_targetid;
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dp->version = (dp_debug_port_id & ADIV5_DP_DPIDR_VERSION_MASK) >> ADIV5_DP_DPIDR_VERSION_OFFSET;
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dp->debug_port_id = dp_debug_port_id;
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dp->target_id = dp_targetid;
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adiv5_dp_init(dp);
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}
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return target_list ? 1U : 0U;
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@ -193,12 +197,12 @@ uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
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uint32_t firmware_swdp_error(ADIv5_DP_t *dp)
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{
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if ((dp->fault && (dp->debug_port_id & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) && dp->dp_low_write) {
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/* On protocoll error target gets deselected.
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if (dp->version >= 2 && dp->dp_low_write) {
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/* On protocol error target gets deselected.
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* With DP Change, another target needs selection.
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* => Reselect with right target! */
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dp_line_reset(dp);
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dp->dp_low_write(dp, ADIV5_DP_TARGETSEL, dp->targetid);
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dp->dp_low_write(dp, ADIV5_DP_TARGETSEL, dp->target_id);
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dp->dp_read(dp, ADIV5_DP_DPIDR);
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/* Exception here is unexpected, so do not catch */
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}
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@ -283,8 +283,19 @@ bool cortexm_probe(ADIv5_AP_t *ap)
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}
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adiv5_ap_ref(ap);
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t->designer_code = ap->designer_code;
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t->part_id = ap->ap_partno;
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if (ap->dp->version >= 2 && ap->dp->target_id != 0) {
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/* Use TARGETID register to identify target */
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const uint16_t tdesigner =
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(ap->dp->target_id & ADIV5_DP_TARGETID_TDESIGNER_MASK) >> ADIV5_DP_TARGETID_TDESIGNER_OFFSET;
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/* convert it to our internal representation, See JEP-106 code list */
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t->designer_code =
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(tdesigner & ADIV5_DP_DESIGNER_JEP106_CONT_MASK) << 1U | (tdesigner & ADIV5_DP_DESIGNER_JEP106_CODE_MASK);
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t->part_id = (ap->dp->target_id & ADIV5_DP_TARGETID_TPARTNO_MASK) >> ADIV5_DP_TARGETID_TPARTNO_OFFSET;
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} else {
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/* Use AP DESIGNER and AP PARTNO to identify target */
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t->designer_code = ap->designer_code;
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t->part_id = ap->partno;
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}
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struct cortexm_priv *priv = calloc(1, sizeof(*priv));
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if (!priv) { /* calloc failed: heap exhaustion */
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DEBUG_WARN("calloc: failed in %s\n", __func__);
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@ -401,10 +412,10 @@ bool cortexm_probe(ADIv5_AP_t *ap)
|
|||
} while (0)
|
||||
#endif
|
||||
|
||||
switch (ap->designer_code) {
|
||||
switch (t->designer_code) {
|
||||
case JEP106_MANUFACTURER_FREESCALE:
|
||||
PROBE(kinetis_probe);
|
||||
if (ap->ap_partno == 0x88c) {
|
||||
if (t->part_id == 0x88c) {
|
||||
t->driver = "MIMXRT10xx(no flash)";
|
||||
target_halt_resume(t, 0);
|
||||
}
|
||||
|
|
@ -444,36 +455,21 @@ bool cortexm_probe(ADIv5_AP_t *ap)
|
|||
case JEP106_MANUFACTURER_SPECULAR:
|
||||
PROBE(lpc11xx_probe); /* LPC845 */
|
||||
break;
|
||||
default:
|
||||
if (ap->designer_code != JEP106_MANUFACTURER_ARM) {
|
||||
/* Report unexpected designers */
|
||||
#if PC_HOSTED == 0
|
||||
gdb_outf("Please report probed device with Designer code 0x%3x and Partno 0x%3x\n", ap->designer_code,
|
||||
ap->ap_partno);
|
||||
#else
|
||||
DEBUG_WARN("Please report probed device with Designer code 0x%3x and Partno 0x%3x\n", ap->designer_code,
|
||||
ap->ap_partno);
|
||||
#endif
|
||||
}
|
||||
if (ap->ap_partno == 0x4c0) { /* Cortex-M0+ ROM */
|
||||
const uint16_t tdesigner =
|
||||
(ap->dp->targetid & ADIV5_DP_TARGETID_TDESIGNER_MASK) >> ADIV5_DP_TARGETID_TDESIGNER_OFFSET;
|
||||
/* convert it to our internal representation, See JEP-106 code list */
|
||||
const uint16_t designer_code = (tdesigner & ADIV5_DP_DESIGNER_JEP106_CONT_MASK) << 1U |
|
||||
(tdesigner & ADIV5_DP_DESIGNER_JEP106_CODE_MASK);
|
||||
if (designer_code == JEP106_MANUFACTURER_RASPBERRY)
|
||||
PROBE(rp_probe);
|
||||
PROBE(lpc11xx_probe); /* LPC8 */
|
||||
} else if (ap->ap_partno == 0x4c3) { /* Cortex-M3 ROM */
|
||||
case JEP106_MANUFACTURER_RASPBERRY:
|
||||
PROBE(rp_probe);
|
||||
break;
|
||||
case JEP106_MANUFACTURER_ARM:
|
||||
if (t->part_id == 0x4c0) { /* Cortex-M0+ ROM */
|
||||
PROBE(lpc11xx_probe); /* LPC8 */
|
||||
} else if (t->part_id == 0x4c3) { /* Cortex-M3 ROM */
|
||||
PROBE(lmi_probe);
|
||||
PROBE(ch32f1_probe);
|
||||
PROBE(stm32f1_probe); /* Care for other STM32F1 clones (?) */
|
||||
PROBE(lpc15xx_probe); /* Thanks to JojoS for testing */
|
||||
PROBE(lpc11xx_probe); /* LPC1343 */
|
||||
} else if (ap->ap_partno == 0x471) { /* Cortex-M0 ROM */
|
||||
PROBE(lpc11xx_probe); /* LPC24C11 */
|
||||
PROBE(stm32f1_probe); /* Care for other STM32F1 clones (?) */
|
||||
PROBE(lpc15xx_probe); /* Thanks to JojoS for testing */
|
||||
} else if (t->part_id == 0x471) { /* Cortex-M0 ROM */
|
||||
PROBE(lpc11xx_probe); /* LPC24C11 */
|
||||
PROBE(lpc43xx_probe);
|
||||
} else if (ap->ap_partno == 0x4c4) { /* Cortex-M4 ROM */
|
||||
} else if (t->part_id == 0x4c4) { /* Cortex-M4 ROM */
|
||||
PROBE(lmi_probe);
|
||||
/* The LPC546xx and LPC43xx parts present with the same AP ROM Part
|
||||
Number, so we need to probe both. Unfortunately, when probing for
|
||||
|
|
@ -483,19 +479,28 @@ bool cortexm_probe(ADIv5_AP_t *ap)
|
|||
probe for the LPC546xx first, which experimentally doesn't harm
|
||||
LPC43xx detection. */
|
||||
PROBE(lpc546xx_probe);
|
||||
|
||||
PROBE(lpc43xx_probe);
|
||||
PROBE(kinetis_probe); /* Older K-series */
|
||||
} else if (ap->ap_partno == 0x4cb) { /* Cortex-M23 ROM */
|
||||
PROBE(gd32f1_probe); /* GD32E23x uses GD32F1 peripherals */
|
||||
} else if (ap->ap_partno == 0x4c0) { /* Cortex-M0+ ROM */
|
||||
PROBE(lpc11xx_probe); /* some of the LPC8xx series, like LPC802 */
|
||||
PROBE(kinetis_probe); /* Older K-series */
|
||||
} else if (t->part_id == 0x4cb) { /* Cortex-M23 ROM */
|
||||
PROBE(gd32f1_probe); /* GD32E23x uses GD32F1 peripherals */
|
||||
}
|
||||
/* Info on PIDR of these parts wanted! */
|
||||
break;
|
||||
case ASCII_CODE_FLAG:
|
||||
/*
|
||||
* these devices enumerate an AP with an empty ascii code,
|
||||
* and have no available designer code elsewhere
|
||||
*/
|
||||
PROBE(sam3x_probe);
|
||||
PROBE(ke04_probe);
|
||||
PROBE(lpc17xx_probe);
|
||||
PROBE(lpc11xx_probe); /* LPC1343 */
|
||||
break;
|
||||
}
|
||||
#if PC_HOSTED == 0
|
||||
gdb_outf("Please report unknown device with Designer %x Part ID %x\n", ap->designer_code, ap->partno);
|
||||
#else
|
||||
DEBUG_WARN("Please report unknown device with Designer %x Part ID %x\n", ap->designer_code, ap->partno);
|
||||
#endif
|
||||
#undef PROBE
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -511,14 +511,14 @@ bool stm32l4_probe(target *t)
|
|||
{
|
||||
ADIv5_AP_t *ap = cortexm_ap(t);
|
||||
uint32_t device_id;
|
||||
if (ap->dp->targetid > 1) { /* STM32L552 has invalid TARGETID 1 */
|
||||
/* todo: cleanup, this does not look correct, nothing in TARGETID register has offset 16 */
|
||||
device_id = (ap->dp->targetid >> 16) & 0xfff;
|
||||
if (ap->dp->version >= 2 && ap->dp->target_id > 1) { /* STM32L552 has invalid TARGETID 1 */
|
||||
/* FIXME: this does not look correct, nothing in TARGETID register has offset 16 */
|
||||
device_id = (ap->dp->target_id >> 16U) & 0xfffU;
|
||||
} else {
|
||||
uint32_t idcode_reg = STM32L4_DBGMCU_IDCODE_PHYS;
|
||||
if (ap->dp->debug_port_id == 0x0Be12477)
|
||||
if (ap->dp->debug_port_id == 0x0be12477U)
|
||||
idcode_reg = STM32L5_DBGMCU_IDCODE_PHYS;
|
||||
device_id = target_mem_read32(t, idcode_reg) & 0xfff;
|
||||
device_id = target_mem_read32(t, idcode_reg) & 0xfffU;
|
||||
DEBUG_INFO("Idcode %08" PRIx32 "\n", device_id);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -117,9 +117,6 @@ struct target_s {
|
|||
/* target-defined options */
|
||||
unsigned target_options;
|
||||
|
||||
uint16_t designer_code;
|
||||
uint16_t part_id;
|
||||
|
||||
void *target_storage;
|
||||
union {
|
||||
bool unsafe_enabled;
|
||||
|
|
@ -144,6 +141,13 @@ struct target_s {
|
|||
|
||||
void *priv;
|
||||
void (*priv_free)(void *);
|
||||
|
||||
/* Target designer and id / partno */
|
||||
uint16_t designer_code;
|
||||
/* targetid partno if available (>= DPv2)
|
||||
* fallback to ap partno
|
||||
*/
|
||||
uint16_t part_id;
|
||||
};
|
||||
|
||||
void target_print_progress(platform_timeout *timeout);
|
||||
|
|
|
|||
Loading…
Reference in New Issue