sys64738
/
blackmagic
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Fix compiling for native probe

This commit is contained in:
James Turton 2021-05-11 09:12:15 +02:00 committed by UweBonnes
parent e4421799ba
commit f880734050
3 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/target/adiv5.c
View File

@ -661,8 +661,8 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
return; return;
} }
DEBUG_INFO("DPIDR 0x%08" PRIx32 " (v%d %srev%d)\n", dp->idcode, DEBUG_INFO("DPIDR 0x%08" PRIx32 " (v%d %srev%d)\n", dp->idcode,
(dp->idcode >> 12) & 0xf, (uint8_t)((dp->idcode >> 12) & 0xf),
(dp->idcode & 0x10000) ? "MINDP " : "", dp->idcode >> 28); (dp->idcode & 0x10000) ? "MINDP " : "", (uint16_t)(dp->idcode >> 28));
volatile uint32_t ctrlstat = 0; volatile uint32_t ctrlstat = 0;
#if PC_HOSTED == 1 #if PC_HOSTED == 1
platform_adiv5_dp_defaults(dp); platform_adiv5_dp_defaults(dp);

2
src/target/cortexm.c
View File

@ -327,7 +327,7 @@ bool cortexm_probe(ADIv5_AP_t *ap)
break; break;
default: default:
if (ap->ap_designer != AP_DESIGNER_ATMEL) /* Protected Atmel device?*/{ if (ap->ap_designer != AP_DESIGNER_ATMEL) /* Protected Atmel device?*/{
DEBUG_WARN("Unexpected CortexM CPUID partno %04x\n", cpuid_partno); DEBUG_WARN("Unexpected CortexM CPUID partno %04" PRIx32 "\n", cpuid_partno);
} }
} }
DEBUG_INFO("CPUID 0x%08" PRIx32 " (%s var %" PRIx32 " rev %" PRIx32 ")\n", DEBUG_INFO("CPUID 0x%08" PRIx32 " (%s var %" PRIx32 " rev %" PRIx32 ")\n",

10
src/target/rp.c
View File

@ -131,14 +131,14 @@ static bool rp_rom_call(target *t, uint32_t *regs, uint32_t cmd,
target_halt_resume(t, false); target_halt_resume(t, false);
if (!timeout) if (!timeout)
return false; return false;
DEBUG_INFO("Call cmd %04x\n", cmd); DEBUG_INFO("Call cmd %04" PRIx32 "\n", cmd);
platform_timeout to; platform_timeout to;
platform_timeout_set(&to, timeout); platform_timeout_set(&to, timeout);
do { do {
if (timeout > 400) if (timeout > 400)
tc_printf(t, "\b%c", spinner[spinindex++ % 4]); tc_printf(t, "\b%c", spinner[spinindex++ % 4]);
if (platform_timeout_is_expired(&to)) { if (platform_timeout_is_expired(&to)) {
DEBUG_WARN("RP Run timout %d ms reached: ", timeout); DEBUG_WARN("RP Run timout %d ms reached: ", (int)timeout);
break; break;
} }
} while (!target_halt_poll(t, NULL)); } while (!target_halt_poll(t, NULL));
@ -146,7 +146,7 @@ static bool rp_rom_call(target *t, uint32_t *regs, uint32_t cmd,
target_regs_read(t, dbg_regs); target_regs_read(t, dbg_regs);
bool ret = ((dbg_regs[REG_PC] &~1) != (ps->_debug_trampoline_end & ~1)); bool ret = ((dbg_regs[REG_PC] &~1) != (ps->_debug_trampoline_end & ~1));
if (ret) { if (ret) {
DEBUG_WARN("rp_rom_call cmd %04x failed, PC %08" PRIx32 "\n", DEBUG_WARN("rp_rom_call cmd %04" PRIx32 " failed, PC %08" PRIx32 "\n",
cmd, dbg_regs[REG_PC]); cmd, dbg_regs[REG_PC]);
} }
return ret; return ret;
@ -181,7 +181,7 @@ static int rp_flash_erase(struct target_flash *f, target_addr addr,
DEBUG_WARN("Unaligned len\n"); DEBUG_WARN("Unaligned len\n");
len = (len + 0xfff) & ~0xfff; len = (len + 0xfff) & ~0xfff;
} }
DEBUG_INFO("Erase addr %08" PRIx32 " len 0x%" PRIx32 "\n", addr, len); DEBUG_INFO("Erase addr %08" PRIx32 " len 0x%" PRIx32 "\n", addr, (uint32_t)len);
target *t = f->t; target *t = f->t;
rp_flash_prepare(t); rp_flash_prepare(t);
struct rp_priv_s *ps = (struct rp_priv_s*)t->target_storage; struct rp_priv_s *ps = (struct rp_priv_s*)t->target_storage;
@ -236,7 +236,7 @@ static int rp_flash_erase(struct target_flash *f, target_addr addr,
int rp_flash_write(struct target_flash *f, int rp_flash_write(struct target_flash *f,
target_addr dest, const void *src, size_t len) target_addr dest, const void *src, size_t len)
{ {
DEBUG_INFO("RP Write %08" PRIx32 " len 0x%" PRIx32 "\n", dest, len); DEBUG_INFO("RP Write %08" PRIx32 " len 0x%" PRIx32 "\n", dest, (uint32_t)len);
if ((dest & 0xff) || (len & 0xff)) { if ((dest & 0xff) || (len & 0xff)) {
DEBUG_WARN("Unaligned erase\n"); DEBUG_WARN("Unaligned erase\n");
return -1; return -1;