sam3x: Update to use new buffered flash interface.
This commit is contained in:
Gareth McMullin
parent
21c209fd8f
commit
fc2f266a13
361
src/sam3x.c
361
src/sam3x.c
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@ -1,7 +1,7 @@
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/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2012 Black Sphere Technologies Ltd.
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* Copyright (C) 2015 Black Sphere Technologies Ltd.
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* Written by Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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@ -18,8 +18,10 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements Atmel SAM3X target specific functions for detecting
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/* This file implements Atmel SAM3/4 target specific functions for detecting
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* the device, providing the XML memory map and Flash memory programming.
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*
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* Supported devices: SAM3N, SAM3S, SAM3U, SAM3X, and SAM4S
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*/
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#include "general.h"
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@ -28,9 +30,10 @@
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#include "command.h"
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#include "gdb_packet.h"
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static int sam3x_flash_erase(target *t, uint32_t addr, size_t len);
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static int sam3x_flash_write(target *t, uint32_t dest,
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const uint8_t *src, size_t len);
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static int sam4_flash_erase(struct target_flash *f, uint32_t addr, size_t len);
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static int sam3_flash_erase(struct target_flash *f, uint32_t addr, size_t len);
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static int sam3x_flash_write(struct target_flash *f, uint32_t dest,
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const void *src, size_t len);
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static bool sam3x_cmd_gpnvm_get(target *t);
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static bool sam3x_cmd_gpnvm_set(target *t, int argc, char *argv[]);
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@ -41,54 +44,6 @@ const struct command_s sam3x_cmd_list[] = {
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{NULL, NULL, NULL}
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};
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static const char sam3x_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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/* "<!DOCTYPE memory-map "
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" PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
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" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"*/
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"<memory-map>"
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" <memory type=\"flash\" start=\"0x80000\" length=\"0x80000\">"
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" <property name=\"blocksize\">0x100</property>"
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" </memory>"
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" <memory type=\"rom\" start=\"0x100000\" length=\"0x200000\"/>"
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" <memory type=\"ram\" start=\"0x20000000\" length=\"0x200000\"/>"
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"</memory-map>";
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static const char sam3n_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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/* "<!DOCTYPE memory-map "
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" PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
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" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"*/
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"<memory-map>"
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" <memory type=\"flash\" start=\"0x400000\" length=\"0x400000\">"
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" <property name=\"blocksize\">0x100</property>"
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" </memory>"
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" <memory type=\"rom\" start=\"0x800000\" length=\"0x400000\"/>"
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" <memory type=\"ram\" start=\"0x20000000\" length=\"0x200000\"/>"
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"</memory-map>";
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static const char sam3u_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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/* "<!DOCTYPE memory-map "
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" PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
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" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"*/
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"<memory-map>"
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" <memory type=\"flash\" start=\"0x80000\" length=\"0x100000\">"
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" <property name=\"blocksize\">0x100</property>"
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" </memory>"
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" <memory type=\"rom\" start=\"0x180000\" length=\"0x200000\"/>"
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" <memory type=\"ram\" start=\"0x20000000\" length=\"0x200000\"/>"
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"</memory-map>";
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static const char sam4s_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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/* "<!DOCTYPE memory-map "
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" PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
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" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"*/
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"<memory-map>"
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" <memory type=\"flash\" start=\"0x400000\" length=\"0x400000\">"
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" <property name=\"blocksize\">0x200</property>"
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" </memory>"
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" <memory type=\"rom\" start=\"0x800000\" length=\"0x400000\"/>"
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" <memory type=\"ram\" start=\"0x20000000\" length=\"0x400000\"/>"
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"</memory-map>";
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/* Enhanced Embedded Flash Controller (EEFC) Register Map */
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#define SAM3N_EEFC_BASE 0x400E0A00
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#define SAM3X_EEFC_BASE(x) (0x400E0A00+((x)*0x400))
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@ -129,6 +84,10 @@ static const char sam4s_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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#define CHIPID_CIDR_EPROC_CM4 (0x07 << 5)
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#define CHIPID_CIDR_EPROC_MASK (0x07 << 5)
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#define CHIPID_CIDR_NVPSIZ_MASK (0x0F << 8)
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#define CHIPID_CIDR_NVPSIZ_8K (0x01 << 8)
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#define CHIPID_CIDR_NVPSIZ_16K (0x02 << 8)
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#define CHIPID_CIDR_NVPSIZ_32K (0x03 << 8)
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#define CHIPID_CIDR_NVPSIZ_64K (0x05 << 8)
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#define CHIPID_CIDR_NVPSIZ_128K (0x07 << 8)
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#define CHIPID_CIDR_NVPSIZ_256K (0x09 << 8)
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#define CHIPID_CIDR_NVPSIZ_512K (0x0A << 8)
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@ -159,23 +118,92 @@ static const char sam4s_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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#define SAM3_PAGE_SIZE 256
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#define SAM4_PAGE_SIZE 512
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struct sam_flash {
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struct target_flash f;
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uint32_t eefc_base;
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uint8_t write_cmd;
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};
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static void sam3_add_flash(target *t,
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uint32_t eefc_base, uint32_t addr, size_t length)
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{
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struct sam_flash *sf = calloc(1, sizeof(*sf));
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struct target_flash *f = &sf->f;
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f->start = addr;
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f->length = length;
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f->blocksize = SAM3_PAGE_SIZE;
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f->erase = sam3_flash_erase;
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f->write = target_flash_write_buffered;
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f->done = target_flash_done_buffered;
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f->write_buf = sam3x_flash_write;
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f->buf_size = SAM3_PAGE_SIZE;
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sf->eefc_base = eefc_base;
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sf->write_cmd = EEFC_FCR_FCMD_EWP;
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target_add_flash(t, f);
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}
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static void sam4_add_flash(target *t,
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uint32_t eefc_base, uint32_t addr, size_t length)
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{
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struct sam_flash *sf = calloc(1, sizeof(*sf));
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struct target_flash *f = &sf->f;
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f->start = addr;
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f->length = length;
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f->blocksize = SAM4_PAGE_SIZE * 8;
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f->erase = sam4_flash_erase;
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f->write = target_flash_write_buffered;
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f->done = target_flash_done_buffered;
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f->write_buf = sam3x_flash_write;
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f->buf_size = SAM4_PAGE_SIZE;
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sf->eefc_base = eefc_base;
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sf->write_cmd = EEFC_FCR_FCMD_WP;
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target_add_flash(t, f);
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}
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static size_t sam_flash_size(uint32_t idcode)
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{
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switch (idcode & CHIPID_CIDR_NVPSIZ_MASK) {
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case CHIPID_CIDR_NVPSIZ_8K:
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return 0x2000;
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case CHIPID_CIDR_NVPSIZ_16K:
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return 0x4000;
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case CHIPID_CIDR_NVPSIZ_32K:
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return 0x8000;
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case CHIPID_CIDR_NVPSIZ_64K:
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return 0x10000;
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case CHIPID_CIDR_NVPSIZ_128K:
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return 0x20000;
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case CHIPID_CIDR_NVPSIZ_256K:
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return 0x40000;
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case CHIPID_CIDR_NVPSIZ_512K:
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return 0x80000;
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case CHIPID_CIDR_NVPSIZ_1024K:
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return 0x100000;
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case CHIPID_CIDR_NVPSIZ_2048K:
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return 0x200000;
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}
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return 0;
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}
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bool sam3x_probe(target *t)
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{
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t->idcode = target_mem_read32(t, SAM3X_CHIPID_CIDR);
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size_t size = sam_flash_size(t->idcode);
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switch (t->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) {
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case CHIPID_CIDR_ARCH_SAM3XxC | CHIPID_CIDR_EPROC_CM3:
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case CHIPID_CIDR_ARCH_SAM3XxE | CHIPID_CIDR_EPROC_CM3:
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case CHIPID_CIDR_ARCH_SAM3XxG | CHIPID_CIDR_EPROC_CM3:
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t->driver = "Atmel SAM3X";
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t->xml_mem_map = sam3x_xml_memory_map;
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t->flash_erase = sam3x_flash_erase;
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t->flash_write = sam3x_flash_write;
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target_add_ram(t, 0x20000000, 0x200000);
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/* 2 Flash memories back-to-back starting at 0x80000 */
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sam3_add_flash(t, SAM3X_EEFC_BASE(0), 0x80000, size/2);
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sam3_add_flash(t, SAM3X_EEFC_BASE(1), 0x80000 + size/2, size/2);
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target_add_commands(t, sam3x_cmd_list, "SAM3X");
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return true;
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}
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t->idcode = target_mem_read32(t, SAM34NSU_CHIPID_CIDR);
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size = sam_flash_size(t->idcode);
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switch (t->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) {
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case CHIPID_CIDR_ARCH_SAM3NxA | CHIPID_CIDR_EPROC_CM3:
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case CHIPID_CIDR_ARCH_SAM3NxB | CHIPID_CIDR_EPROC_CM3:
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@ -184,26 +212,40 @@ bool sam3x_probe(target *t)
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case CHIPID_CIDR_ARCH_SAM3SxB | CHIPID_CIDR_EPROC_CM3:
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case CHIPID_CIDR_ARCH_SAM3SxC | CHIPID_CIDR_EPROC_CM3:
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t->driver = "Atmel SAM3N/S";
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t->xml_mem_map = sam3n_xml_memory_map;
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t->flash_erase = sam3x_flash_erase;
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t->flash_write = sam3x_flash_write;
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target_add_commands(t, sam3x_cmd_list, "SAM3N");
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target_add_ram(t, 0x20000000, 0x200000);
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/* These devices only have a single bank */
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size = sam_flash_size(t->idcode);
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sam3_add_flash(t, SAM3N_EEFC_BASE, 0x400000, size);
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target_add_commands(t, sam3x_cmd_list, "SAM3N/S");
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return true;
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case CHIPID_CIDR_ARCH_SAM3UxC | CHIPID_CIDR_EPROC_CM3:
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case CHIPID_CIDR_ARCH_SAM3UxE | CHIPID_CIDR_EPROC_CM3:
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t->driver = "Atmel SAM3U";
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t->xml_mem_map = sam3u_xml_memory_map;
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t->flash_erase = sam3x_flash_erase;
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t->flash_write = sam3x_flash_write;
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target_add_ram(t, 0x20000000, 0x200000);
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/* One flash up to 512K at 0x80000 */
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sam3_add_flash(t, SAM3U_EEFC_BASE(0), 0x80000, MIN(size, 0x80000));
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if (size >= 0x80000) {
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/* Larger devices have a second bank at 0x100000 */
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sam3_add_flash(t, SAM3U_EEFC_BASE(1),
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0x100000, 0x80000);
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}
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target_add_commands(t, sam3x_cmd_list, "SAM3U");
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return true;
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case CHIPID_CIDR_ARCH_SAM4SxA | CHIPID_CIDR_EPROC_CM4:
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case CHIPID_CIDR_ARCH_SAM4SxB | CHIPID_CIDR_EPROC_CM4:
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case CHIPID_CIDR_ARCH_SAM4SxC | CHIPID_CIDR_EPROC_CM4:
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t->driver = "Atmel SAM4S";
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t->xml_mem_map = sam4s_xml_memory_map;
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t->flash_erase = sam3x_flash_erase;
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t->flash_write = sam3x_flash_write;
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target_add_ram(t, 0x20000000, 0x400000);
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size_t size = sam_flash_size(t->idcode);
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if (size <= 0x80000) {
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/* Smaller devices have a single bank */
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sam4_add_flash(t, SAM4S_EEFC_BASE(0), 0x400000, size);
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} else {
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/* Larger devices are split evenly between 2 */
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sam4_add_flash(t, SAM4S_EEFC_BASE(0), 0x400000, size/2);
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sam4_add_flash(t, SAM4S_EEFC_BASE(1),
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0x400000 + size/2, size/2);
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}
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target_add_commands(t, sam3x_cmd_list, "SAM4S");
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return true;
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}
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@ -227,191 +269,70 @@ sam3x_flash_cmd(target *t, uint32_t base, uint8_t cmd, uint16_t arg)
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return sr & EEFC_FSR_ERROR;
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}
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static uint32_t
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sam3x_flash_base(target *t, uint32_t addr, uint32_t *offset)
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static uint32_t sam3x_flash_base(target *t)
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{
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if (strcmp(t->driver, "Atmel SAM3X") == 0) {
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uint32_t half = -1;
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switch (t->idcode & CHIPID_CIDR_NVPSIZ_MASK) {
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case CHIPID_CIDR_NVPSIZ_128K:
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half = 0x00090000;
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break;
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case CHIPID_CIDR_NVPSIZ_256K:
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half = 0x000A0000;
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break;
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case CHIPID_CIDR_NVPSIZ_512K:
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half = 0x000C0000;
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break;
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}
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if (addr > half) {
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if (offset)
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*offset = addr - half;
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return SAM3X_EEFC_BASE(1);
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} else {
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if (offset)
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*offset = addr - 0x80000;
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return SAM3X_EEFC_BASE(0);
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}
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return SAM3X_EEFC_BASE(0);
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}
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/* The SAM3U has a constant split between both banks */
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if (strcmp(t->driver, "Atmel SAM3U") == 0) {
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if (addr >= 0x100000) {
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if(offset)
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*offset = addr - 0x100000;
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return SAM3U_EEFC_BASE(1);
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} else {
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if(offset)
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*offset = addr - 0x80000;
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return SAM3U_EEFC_BASE(0);
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}
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return SAM3U_EEFC_BASE(0);
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}
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if (strcmp(t->driver, "Atmel SAM4S") == 0) {
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uint32_t half = -1;
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switch (t->idcode & CHIPID_CIDR_NVPSIZ_MASK) {
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case CHIPID_CIDR_NVPSIZ_128K:
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case CHIPID_CIDR_NVPSIZ_256K:
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case CHIPID_CIDR_NVPSIZ_512K:
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if (offset)
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*offset = addr - 0x400000;
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return SAM4S_EEFC_BASE(0);
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case CHIPID_CIDR_NVPSIZ_1024K:
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half = 0x480000;
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break;
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case CHIPID_CIDR_NVPSIZ_2048K:
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half = 0x500000;
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break;
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}
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if (addr >= half) {
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if (offset)
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*offset = addr - half;
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return SAM4S_EEFC_BASE(1);
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} else {
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if (offset)
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*offset = addr - 0x400000;
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return SAM4S_EEFC_BASE(0);
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}
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return SAM4S_EEFC_BASE(0);
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}
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/* SAM3N device */
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if (offset)
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*offset = addr - 0x400000;
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return SAM3N_EEFC_BASE;
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}
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static int sam3x_flash_erase(target *t, uint32_t addr, size_t len)
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static int sam4_flash_erase(struct target_flash *f, uint32_t addr, size_t len)
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{
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uint32_t offset;
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uint32_t base = sam3x_flash_base(t, addr, &offset);
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target *t = f->t;
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uint32_t base = ((struct sam_flash *)f)->eefc_base;
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uint32_t offset = addr - f->start;
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/* The SAM4S is the only supported device with a page erase command.
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* Erasing is done in 8-page chunks. arg[15:2] contains the page
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* number and arg[1:0] contains 0x1, indicating 8-page chunks.
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*/
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if (strcmp(t->driver, "Atmel SAM4S") == 0) {
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unsigned chunk = offset / SAM4_PAGE_SIZE;
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/* Fail if the start address is not 8-page-aligned. */
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if (chunk % 8 != 0)
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return -1;
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/* Note that the length might not be a multiple of 8 pages.
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* In this case, we will erase a few extra pages at the end.
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*/
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while (len > 0) {
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int16_t arg = chunk | 0x1;
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if(sam3x_flash_cmd(t, base, EEFC_FCR_FCMD_EPA, arg))
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return -1;
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len -= SAM4_PAGE_SIZE * 8;
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addr += SAM4_PAGE_SIZE * 8;
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chunk += 8;
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}
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return 0;
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}
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/* The SAM3X/SAM3N don't really have a page erase function.
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* This Erase/Write page is the best we have, so we write with all
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* ones. This does waste time, but what can we do?
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*/
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unsigned chunk = offset / SAM3_PAGE_SIZE;
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uint8_t buf[SAM3_PAGE_SIZE];
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memset(buf, 0xff, sizeof(buf));
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/* Only do this once, since it doesn't change. */
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target_mem_write(t, addr, buf, SAM3_PAGE_SIZE);
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unsigned chunk = offset / SAM4_PAGE_SIZE;
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|
||||
while (len) {
|
||||
if(sam3x_flash_cmd(t, base, EEFC_FCR_FCMD_EWP, chunk))
|
||||
int16_t arg = chunk | 0x1;
|
||||
if(sam3x_flash_cmd(t, base, EEFC_FCR_FCMD_EPA, arg))
|
||||
return -1;
|
||||
|
||||
len -= SAM3_PAGE_SIZE;
|
||||
addr += SAM3_PAGE_SIZE;
|
||||
chunk++;
|
||||
len -= f->blocksize;
|
||||
chunk += 8;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sam3x_flash_write(target *t, uint32_t dest,
|
||||
const uint8_t *src, size_t len)
|
||||
static int sam3_flash_erase(struct target_flash *f, uint32_t addr, size_t len)
|
||||
{
|
||||
unsigned page_size;
|
||||
if (strcmp(t->driver, "Atmel SAM4S") == 0) {
|
||||
page_size = SAM4_PAGE_SIZE;
|
||||
} else {
|
||||
page_size = SAM3_PAGE_SIZE;
|
||||
}
|
||||
uint32_t offset;
|
||||
uint32_t base = sam3x_flash_base(t, dest, &offset);
|
||||
uint8_t buf[page_size];
|
||||
unsigned first_chunk = offset / page_size;
|
||||
unsigned last_chunk = (offset + len - 1) / page_size;
|
||||
offset %= page_size;
|
||||
dest -= offset;
|
||||
/* The SAM3X/SAM3N don't really have a page erase function.
|
||||
* We do nothing here and use Erase/Write page in flash_write.
|
||||
*/
|
||||
(void)f; (void)addr; (void)len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (unsigned chunk = first_chunk; chunk <= last_chunk; chunk++) {
|
||||
static int sam3x_flash_write(struct target_flash *f, uint32_t dest,
|
||||
const void *src, size_t len)
|
||||
{
|
||||
target *t = f->t;
|
||||
struct sam_flash *sf = (struct sam_flash *)f;
|
||||
uint32_t base = sf->eefc_base;
|
||||
unsigned chunk = (dest - f->start) / f->buf_size;
|
||||
|
||||
DEBUG("chunk %u len %zu\n", chunk, len);
|
||||
/* first and last chunk may require special handling */
|
||||
if ((chunk == first_chunk) || (chunk == last_chunk)) {
|
||||
|
||||
/* fill with all ff to avoid sector rewrite corrupting other writes */
|
||||
memset(buf, 0xff, sizeof(buf));
|
||||
|
||||
/* copy as much as fits */
|
||||
size_t copylen = page_size - offset;
|
||||
if (copylen > len)
|
||||
copylen = len;
|
||||
memcpy(&buf[offset], src, copylen);
|
||||
|
||||
/* update to suit */
|
||||
len -= copylen;
|
||||
src += copylen;
|
||||
offset = 0;
|
||||
} else {
|
||||
|
||||
/* interior chunk, must be aligned and full-sized */
|
||||
memcpy(buf, src, page_size);
|
||||
len -= page_size;
|
||||
src += page_size;
|
||||
}
|
||||
|
||||
target_mem_write(t, dest, buf, page_size);
|
||||
if(sam3x_flash_cmd(t, base, EEFC_FCR_FCMD_WP, chunk))
|
||||
return -1;
|
||||
}
|
||||
target_mem_write(t, dest, src, len);
|
||||
if(sam3x_flash_cmd(t, base, sf->write_cmd, chunk))
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool sam3x_cmd_gpnvm_get(target *t)
|
||||
{
|
||||
uint32_t base = sam3x_flash_base(t, 0, NULL);
|
||||
uint32_t base = sam3x_flash_base(t);
|
||||
|
||||
sam3x_flash_cmd(t, base, EEFC_FCR_FCMD_GGPB, 0);
|
||||
gdb_outf("GPNVM: 0x%08X\n", target_mem_read32(t, EEFC_FRR(base)));
|
||||
|
|
@ -422,7 +343,7 @@ static bool sam3x_cmd_gpnvm_get(target *t)
|
|||
static bool sam3x_cmd_gpnvm_set(target *t, int argc, char *argv[])
|
||||
{
|
||||
uint32_t bit, cmd;
|
||||
uint32_t base = sam3x_flash_base(t, 0, NULL);
|
||||
uint32_t base = sam3x_flash_base(t);
|
||||
|
||||
if (argc != 3) {
|
||||
gdb_out("usage: monitor gpnvm_set <bit> <val>\n");
|
||||
|
|
|
|||
Loading…
Reference in New Issue