cortexm: Read CPUID to identify core version
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@ -294,7 +294,6 @@ bool cortexm_probe(ADIv5_AP_t *ap, bool forced)
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}
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adiv5_ap_ref(ap);
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uint32_t identity = ap->idr & 0xff;
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struct cortexm_priv *priv = calloc(1, sizeof(*priv));
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if (!priv) { /* calloc failed: heap exhaustion */
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DEBUG_WARN("calloc: failed in %s\n", __func__);
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@ -310,18 +309,37 @@ bool cortexm_probe(ADIv5_AP_t *ap, bool forced)
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t->mem_write = cortexm_mem_write;
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t->driver = cortexm_driver_str;
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switch (identity) {
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case 0x11: /* M3/M4 */
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t->core = "M3/M4";
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uint32_t cpuid = target_mem_read32(t, CORTEXM_CPUID);
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uint16_t partno = (cpuid >> 4) & 0xfff;
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switch (partno) {
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case 0xd21:
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t->core = "M33";
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break;
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case 0x21: /* M0 */
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t->core = "M0";
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case 0xd20:
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t->core = "M23";
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break;
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case 0x31: /* M0+ */
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case 0xc23:
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t->core = "M3";
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break;
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case 0xc24:
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t->core = "M4";
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break;
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case 0xc27:
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t->core = "M7";
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break;
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case 0xc60:
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t->core = "M0+";
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break;
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case 0x01: /* M7 */
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t->core = "M7";
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case 0xc20:
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t->core = "M0";
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break;
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}
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@ -28,6 +28,7 @@ extern long cortexm_wait_timeout;
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#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000)
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#define CORTEXM_CPUID (CORTEXM_SCS_BASE + 0xD00)
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#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C)
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#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28)
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#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C)
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