cortexm: Read CPUID to identify core version

This commit is contained in:
Fredrik Ahlberg 2020-07-12 12:08:22 +02:00
parent 39a20d78ff
commit fcd945a529
2 changed files with 28 additions and 9 deletions

View File

@ -294,7 +294,6 @@ bool cortexm_probe(ADIv5_AP_t *ap, bool forced)
}
adiv5_ap_ref(ap);
uint32_t identity = ap->idr & 0xff;
struct cortexm_priv *priv = calloc(1, sizeof(*priv));
if (!priv) { /* calloc failed: heap exhaustion */
DEBUG_WARN("calloc: failed in %s\n", __func__);
@ -310,18 +309,37 @@ bool cortexm_probe(ADIv5_AP_t *ap, bool forced)
t->mem_write = cortexm_mem_write;
t->driver = cortexm_driver_str;
switch (identity) {
case 0x11: /* M3/M4 */
t->core = "M3/M4";
uint32_t cpuid = target_mem_read32(t, CORTEXM_CPUID);
uint16_t partno = (cpuid >> 4) & 0xfff;
switch (partno) {
case 0xd21:
t->core = "M33";
break;
case 0x21: /* M0 */
t->core = "M0";
case 0xd20:
t->core = "M23";
break;
case 0x31: /* M0+ */
case 0xc23:
t->core = "M3";
break;
case 0xc24:
t->core = "M4";
break;
case 0xc27:
t->core = "M7";
break;
case 0xc60:
t->core = "M0+";
break;
case 0x01: /* M7 */
t->core = "M7";
case 0xc20:
t->core = "M0";
break;
}

View File

@ -28,6 +28,7 @@ extern long cortexm_wait_timeout;
#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000)
#define CORTEXM_CPUID (CORTEXM_SCS_BASE + 0xD00)
#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C)
#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28)
#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C)