target/renesas: add rv40 flash support
This commit is contained in:
Rafael Silva
Rachel Mant
parent
a67fe703e4
commit
fcfbc0fdf1
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@ -176,9 +176,92 @@ typedef enum {
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#define RENESAS_FMIFRT_MCUVER(frt) (frt + 0x44UL) /* MCUVER Register offset from Flash Root Table */
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/* System Control OCD Control */
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#define RENESAS_SYOCDCR 0x4001E40EUL /* System Control OCD Control Register */
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#define SYOCDCR_DBGEN (1 << 7) /* Debug Enable */
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#define SYSC_BASE 0x4001E000UL
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#define SYSC_SYOCDCR (SYSC_BASE + 0x40EU) /* System Control OCD Control Register */
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#define SYOCDCR_DBGEN (1U << 7U) /* Debug Enable */
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#define SYSC_FWEPROR (SYSC_BASE + 0x416U) /* Flash P/E Protect Register */
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#define SYSC_FWEPROR_PERMIT (0x01U)
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#define SYSC_FWEPROR_PROHIBIT (0x10U)
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/* Flash Memory Control */
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#define RENESAS_CF_END (0x00200000UL)
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#define FENTRYR_KEY_OFFSET 8U
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#define FENTRYR_KEY (0xAAU << FENTRYR_KEY_OFFSET)
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#define FENTRYR_PE_CF (1U)
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#define FENTRYR_PE_DF (1U << 7U)
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/* Renesas RA MCUs can have one of two kinds of flash memory, MF3/4 and RV40 */
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/* MF3/4 Flash */
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/*
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* MF3/4 Flash Memory Specifications
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* Block Size: Code area: 2 KB (exept RA2A1 is 1KB), Data area: 1 KB
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* Program/Erase unit Program: Code area: 64 bits, Data area: 8 bits
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* Erase: 1 block
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*/
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#define MF3_CF_BLOCK_SIZE (0x800U)
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#define MF3_RA2A1_CF_BLOCK_SIZE (0x400U)
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#define MF3_DF_BLOCK_SIZE (0x400U)
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#define MF3_CF_WRITE_SIZE (0x40U)
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#define MF3_DF_WRITE_SIZE (0x1U)
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/* RV40 Flash */
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/*
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* RV40F Flash Memory Specifications
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* Block Size: Code area: 8 KB/32KB Data area: 64 Bytes
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* Program/Erase unit Program: Code area: 128 Bytes, Data area: 4/8/16 Bytes
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* Erase: 1 block
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*/
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#define RV40_CF_REGION0_SIZE (0x10000UL)
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#define RV40_CF_REGION0_BLOCK_SIZE (0x2000U)
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#define RV40_CF_REGION1_BLOCK_SIZE (0x8000U)
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#define RV40_DF_BLOCK_SIZE (0x40U)
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#define RV40_CF_WRITE_SIZE (0x80U)
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#define RV40_DF_WRITE_SIZE (0x4U)
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/* RV40 Flash Commands */
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#define RV40_CMD 0x407E0000UL
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#define RV40_CMD_PROGRAM (0xE8U)
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#define RV40_CMD_PROGRAM_CF (0x80U)
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#define RV40_CMD_PROGRAM_DF (0x02U)
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#define RV40_CMD_BLOCK_ERASE (0x20U)
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#define RV40_CMD_PE_SUSPEND (0xB0U)
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#define RV40_CMD_PE_RESUME (0xD0U)
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#define RV40_CMD_STATUS_CLEAR (0x50U)
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#define RV40_CMD_FORCED_STOP (0xB3U)
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#define RV40_CMD_BLANK_CHECK (0x71U)
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#define RV40_CMD_CONFIG_SET_1 (0x40U)
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#define RV40_CMD_CONFIG_SET_2 (0x08U)
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#define RV40_CMD_LOCK_BIT_PGM (0x77U)
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#define RV40_CMD_LOCK_BIT_READ (0x71U)
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#define RV40_CMD_FINAL (0xD0U)
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#define RV40_BASE 0x407FE000UL
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#define RV40_FSTATR (RV40_BASE + 0x80U) /* Flash Status */
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#define RV40_FSTATR_RDY (1U << 15U) /* Flash Ready */
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#define RV40_FSTATR_DBFULL (1U << 10U) /* Data Buffer Full */
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#define RV40_FSADDR (RV40_BASE + 0x30U)
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#define RV40_FMEPROT (RV40_BASE + 0x44U)
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#define RV40_FMEPROT_LOCK (0xD901U)
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#define RV40_FMEPROT_UNLOCK (0xD900U)
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#define RV40_FENTRYR (RV40_BASE + 0x84U)
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#define RV40_FENTRYR_KEY_OFFSET 8U
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#define RV40_FENTRYR_KEY (0xAAU << RV40_FENTRYR_KEY_OFFSET)
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#define RV40_FENTRYR_PE_CF (1U)
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#define RV40_FENTRYR_PE_DF (1U << 7U)
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#define RV40_FCPSR (RV40_BASE + 0xE0U)
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#define RV40_FCPSR_ESUSPMD 1U
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#define RENESAS_CF_END (0x00200000UL) /* End of Flash (maximum possible accross families) */
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static bool renesas_uid(target *t, int argc, const char **argv);
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@ -187,6 +270,12 @@ const struct command_s renesas_cmd_list[] = {
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{NULL, NULL, NULL},
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};
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typedef struct renesas_priv {
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uint8_t pnr[17]; /* 16-byte PNR + 1-byte null termination */
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pnr_series_t series;
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uint32_t flash_root_table; /* if applicable */
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} renesas_priv_s;
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static uint32_t renesas_fmifrt_read(target *t)
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{
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return target_mem_read32(t, RENESAS_FMIFRT);
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@ -262,27 +351,264 @@ static uint32_t renesas_flash_size(const uint8_t *pnr)
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}
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}
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static int renesas_flash_erase(target_flash_s *f, target_addr_t addr, size_t len)
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static int renesas_enter_flash_mode(target *t)
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{
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target_reset(t);
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/* permit flash operations */
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target_mem_write8(t, SYSC_FWEPROR, SYSC_FWEPROR_PERMIT);
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return 0;
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}
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static int renesas_flash_write(target_flash_s *f, target_addr_t dest, const void *src, size_t len) {
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typedef enum pe_mode {
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PE_MODE_READ,
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PE_MODE_CF,
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PE_MODE_DF,
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} pe_mode_e;
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static bool renesas_rv40_pe_mode(target *t, pe_mode_e pe_mode)
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{
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/* See "Transition to Code Flash P/E Mode": Section 47.9.3.3 of the RA6M4 manual R01UH0890EJ0100. */
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renesas_priv_s *priv_storage = (renesas_priv_s *)t->target_storage;
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if (!priv_storage)
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return false;
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bool has_fmeprot = false; /* Code Flash P/E Mode Entry Protection */
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switch (priv_storage->series) {
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case PNR_SERIES_RA4E1:
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case PNR_SERIES_RA4M2:
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case PNR_SERIES_RA4M3:
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case PNR_SERIES_RA6M4:
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case PNR_SERIES_RA6M5:
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case PNR_SERIES_RA6E1:
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case PNR_SERIES_RA6T2:
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has_fmeprot = true;
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default:
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break;
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}
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if (has_fmeprot)
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target_mem_write16(t, RV40_FMEPROT, RV40_FMEPROT_UNLOCK);
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/* Set PE/READ mode */
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uint16_t fentryr = 0;
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switch (pe_mode) {
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case PE_MODE_CF:
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fentryr |= FENTRYR_PE_CF;
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break;
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case PE_MODE_DF:
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fentryr |= FENTRYR_PE_DF;
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break;
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default:
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break;
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}
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target_mem_write16(t, RV40_FENTRYR, FENTRYR_KEY | fentryr);
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platform_timeout timeout;
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platform_timeout_set(&timeout, 10);
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/* Wait for the operation to complete or timeout, Read FENTRYR until it has been set */
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while (target_mem_read16(t, RV40_FENTRYR) != fentryr) {
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if (target_check_error(t) || platform_timeout_is_expired(&timeout))
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return false;
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};
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if (has_fmeprot && pe_mode == PE_MODE_READ) {
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target_mem_write16(t, RV40_FMEPROT, RV40_FMEPROT_LOCK);
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}
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return true;
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}
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/* !TODO: implement blank check */
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static int renesas_rv40_flash_erase(target_flash_s *f, target_addr_t addr, size_t len)
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{
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target *t = f->t;
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/* permit flash operations */
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target_mem_write8(t, SYSC_FWEPROR, SYSC_FWEPROR_PERMIT);
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/* code flash or data flash operation */
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const bool code_flash = addr < RENESAS_CF_END;
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size_t num_blocks;
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uint32_t start_address;
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/* determine the number of blocks to erase */
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if (code_flash) {
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if (addr < RV40_CF_REGION0_SIZE) {
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/* region 0 - 8k blocks */
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start_address = addr & ~(RV40_CF_REGION0_BLOCK_SIZE - 1); /* align to region 0 block */
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num_blocks = (RV40_CF_REGION0_SIZE - start_address) / RV40_CF_REGION0_BLOCK_SIZE;
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if (addr + len > RV40_CF_REGION0_SIZE) {
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/* region 1 - 32k blocks */
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size_t region_len = (addr + len - RV40_CF_REGION0_SIZE);
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/* this may have lead to some of the flash bytes requested not being erased, align to region 1 block size */
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region_len += RV40_CF_REGION1_BLOCK_SIZE - region_len % RV40_CF_REGION1_BLOCK_SIZE;
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num_blocks += region_len / RV40_CF_REGION1_BLOCK_SIZE;
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}
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} else {
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/* region 1 - 32k blocks */
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start_address = addr & ~(RV40_CF_REGION1_BLOCK_SIZE - 1); /* align to region 1 block */
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/* this may have lead to some of the flash bytes requested not being erased, align to region 1 block size */
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len += RV40_CF_REGION1_BLOCK_SIZE - len % RV40_CF_REGION1_BLOCK_SIZE;
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num_blocks = len / RV40_CF_REGION1_BLOCK_SIZE;
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}
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} else {
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start_address = addr & ~(RV40_DF_BLOCK_SIZE - 1);
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/* this may have lead to some of the flash bytes requested not being erased, align to df block size */
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len += RV40_DF_BLOCK_SIZE - len % RV40_DF_BLOCK_SIZE;
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num_blocks = len / RV40_DF_BLOCK_SIZE;
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}
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/* Transition to PE mode */
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const pe_mode_e pe_mode = code_flash ? PE_MODE_CF : PE_MODE_DF;
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if (!renesas_rv40_pe_mode(t, pe_mode))
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return -1;
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/* Set Erasure Priority Mode */
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target_mem_write16(t, RV40_FCPSR, RV40_FCPSR_ESUSPMD);
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while (num_blocks) {
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/* Set block start address*/
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target_mem_write32(t, RV40_FSADDR, start_address);
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/* increment block address */
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if (code_flash)
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start_address +=
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start_address < RV40_CF_REGION0_SIZE ? RV40_CF_REGION0_BLOCK_SIZE : RV40_CF_REGION1_BLOCK_SIZE;
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else
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start_address += RV40_DF_BLOCK_SIZE;
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num_blocks--;
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/* Issue two part Block Erase commands */
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target_mem_write8(t, RV40_CMD, RV40_CMD_BLOCK_ERASE);
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target_mem_write8(t, RV40_CMD, RV40_CMD_FINAL);
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/* according to reference manual the max erase time for a 32K block is around 1040ms
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* this is with a FCLK of 4MHz
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*/
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platform_timeout timeout;
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platform_timeout_set(&timeout, 1100);
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/* Wait until the operation has completed or timeout */
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/* Read FRDY bit until it has been set to 1 indicating that the current operation is complete.*/
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while (!(target_mem_read32(t, RV40_FSTATR) & RV40_FSTATR_RDY)) {
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if (target_check_error(t) || platform_timeout_is_expired(&timeout))
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return -1;
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};
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}
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/* return to read mode */
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renesas_rv40_pe_mode(t, PE_MODE_READ);
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return 0;
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}
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static void renesas_add_flash(target *t, target_addr_t addr, size_t length, size_t page_size)
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static int renesas_rv40_flash_write(target_flash_s *f, target_addr_t dest, const void *src, size_t len)
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{
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target *t = f->t;
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/* permit flash operations */
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target_mem_write8(t, SYSC_FWEPROR, SYSC_FWEPROR_PERMIT);
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/* code flash or data flash operation */
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const bool code_flash = dest < RENESAS_CF_END;
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/* write size for code flash / data flash */
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const uint8_t write_size = code_flash ? RV40_CF_WRITE_SIZE : RV40_DF_WRITE_SIZE;
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if (dest % write_size || len % write_size) /* dest/len must be aligned to write_size */
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return -1;
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/* transition to PE mode */
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const pe_mode_t pe_mode = code_flash ? PE_MODE_CF : PE_MODE_DF;
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if (!renesas_rv40_pe_mode(t, pe_mode))
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return -1;
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while (len) {
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/* set block start address */
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target_mem_write32(t, RV40_FSADDR, dest);
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/* increment destination address */
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dest += write_size;
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len -= write_size;
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/* issue two part Write commands */
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target_mem_write8(t, RV40_CMD, RV40_CMD_PROGRAM);
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target_mem_write8(t, RV40_CMD, (uint8_t)(write_size / 2U));
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/* according to reference manual the data buffer full time for 2 bytes is 2 usec.
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* this is with a FCLK of 4MHz
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* a complete should take less than 1 msec.
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*/
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platform_timeout timeout;
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platform_timeout_set(&timeout, 10);
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/* write one chunk */
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for (size_t i = 0U; i < (write_size / 2U); i++) {
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/* copy data from source address to destination */
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target_mem_write16(t, RV40_CMD, *(uint16_t *)src);
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while (target_mem_read32(t, RV40_FSTATR) & RV40_FSTATR_DBFULL) {
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if (target_check_error(t) || platform_timeout_is_expired(&timeout))
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return -1;
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};
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/* 2 bytes of data */
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src += 2U;
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}
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/* issue write end command */
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target_mem_write8(t, RV40_CMD, RV40_CMD_FINAL);
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/* wait until the operation has completed or timeout */
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/* read FRDY bit until it has been set to 1 indicating that the current operation is complete.*/
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while (!(target_mem_read32(t, RV40_FSTATR) & RV40_FSTATR_RDY)) {
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if (target_check_error(t) || platform_timeout_is_expired(&timeout))
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return -1;
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};
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}
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/* return to read mode*/
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renesas_rv40_pe_mode(t, PE_MODE_READ);
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return 0;
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}
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static void renesas_add_rv40_flash(target *t, target_addr_t addr, size_t length)
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{
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target_flash_s *f = calloc(1, sizeof(*f));
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if (!f) /* calloc failed: heap exhaustion */
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return;
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const bool code_flash = addr < RENESAS_CF_END;
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f->start = addr;
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f->length = length;
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f->erased = 0xffU;
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f->blocksize = page_size;
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f->erase = renesas_flash_erase;
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f->write = renesas_flash_write;
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f->erase = renesas_rv40_flash_erase;
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f->write = renesas_rv40_flash_write;
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if (code_flash) {
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f->blocksize = RV40_CF_REGION1_BLOCK_SIZE;
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f->writebufsize = RV40_CF_WRITE_SIZE * 8U;
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f->writesize = RV40_CF_WRITE_SIZE;
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} else {
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f->blocksize = RV40_DF_BLOCK_SIZE;
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f->writebufsize = RV40_DF_BLOCK_SIZE * 8U;
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f->writesize = RV40_DF_WRITE_SIZE;
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}
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target_add_flash(t, f);
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}
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@ -333,7 +659,6 @@ static void renesas_add_flash(target *t, target_addr_t addr, size_t length)
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case PNR_SERIES_RA6M5:
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case PNR_SERIES_RA6T1:
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case PNR_SERIES_RA6T2:
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t->enter_flash_mode = renesas_enter_flash_mode;
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return renesas_add_rv40_flash(t, addr, length);
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default:
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@ -443,85 +768,85 @@ bool renesas_probe(target *t)
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case PNR_SERIES_RA2L1:
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case PNR_SERIES_RA2A1:
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case PNR_SERIES_RA4M1:
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renesas_add_flash(t, 0x40100000, 8UL * 1024UL, 64); /* Data flash memory 8 KB 0x40100000 */
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target_add_ram(t, 0x20000000, 32UL * 1024UL); /* SRAM 32 KB 0x20000000 */
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renesas_add_flash(t, 0x40100000, 8UL * 1024UL); /* Data flash memory 8 KB 0x40100000 */
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target_add_ram(t, 0x20000000, 32UL * 1024UL); /* SRAM 32 KB 0x20000000 */
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break;
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case PNR_SERIES_RA2E1:
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renesas_add_flash(t, 0x40100000, 4UL * 1024UL, 64); /* Data flash memory 4 KB 0x40100000 */
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target_add_ram(t, 0x20004000, 16UL * 1024UL); /* SRAM 16 KB 0x20004000 */
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renesas_add_flash(t, 0x40100000, 4UL * 1024UL); /* Data flash memory 4 KB 0x40100000 */
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target_add_ram(t, 0x20004000, 16UL * 1024UL); /* SRAM 16 KB 0x20004000 */
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break;
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case PNR_SERIES_RA2E2:
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renesas_add_flash(t, 0x40100000, 2UL * 1024UL, 64); /* Data flash memory 2 KB 0x40100000 */
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target_add_ram(t, 0x20004000, 8UL * 1024UL); /* SRAM 8 KB 0x20004000 */
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renesas_add_flash(t, 0x40100000, 2UL * 1024UL); /* Data flash memory 2 KB 0x40100000 */
|
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target_add_ram(t, 0x20004000, 8UL * 1024UL); /* SRAM 8 KB 0x20004000 */
|
||||
break;
|
||||
|
||||
case PNR_SERIES_RA4M2:
|
||||
case PNR_SERIES_RA4M3:
|
||||
case PNR_SERIES_RA4E1:
|
||||
renesas_add_flash(t, 0x08000000, 8UL * 1024UL, 64); /* Data flash memory 8 KB 0x08000000 */
|
||||
target_add_ram(t, 0x20000000, 128UL * 1024UL); /* SRAM 128 KB 0x20000000 */
|
||||
target_add_ram(t, 0x28000000, 1024UL); /* Standby SRAM 1 KB 0x28000000 */
|
||||
renesas_add_flash(t, 0x08000000, 8UL * 1024UL); /* Data flash memory 8 KB 0x08000000 */
|
||||
target_add_ram(t, 0x20000000, 128UL * 1024UL); /* SRAM 128 KB 0x20000000 */
|
||||
target_add_ram(t, 0x28000000, 1024UL); /* Standby SRAM 1 KB 0x28000000 */
|
||||
break;
|
||||
|
||||
case PNR_SERIES_RA4W1:
|
||||
renesas_add_flash(t, 0x40100000, 8UL * 1024UL, 64); /* Data flash memory 8 KB 0x40100000 */
|
||||
target_add_ram(t, 0x20000000, 96UL * 1024UL); /* SRAM 96 KB 0x20000000 */
|
||||
renesas_add_flash(t, 0x40100000, 8UL * 1024UL); /* Data flash memory 8 KB 0x40100000 */
|
||||
target_add_ram(t, 0x20000000, 96UL * 1024UL); /* SRAM 96 KB 0x20000000 */
|
||||
break;
|
||||
|
||||
case PNR_SERIES_RA6M1:
|
||||
/* conflicting information in the datasheet, here be dragons */
|
||||
renesas_add_flash(t, 0x40100000, 8UL * 1024UL, 64); /* Data flash memory 8 KB 0x40100000 */
|
||||
target_add_ram(t, 0x20000000, 128UL * 1024UL); /* SRAM 128 KB 0x20000000 */
|
||||
target_add_ram(t, 0x1FFE0000, 128UL * 1024UL); /* SRAMHS 128 KB 0x1FFE0000 */
|
||||
target_add_ram(t, 0x200FE000, 8UL * 1024UL); /* Standby SRAM 8 KB 0x200FE000 */
|
||||
renesas_add_flash(t, 0x40100000, 8UL * 1024UL); /* Data flash memory 8 KB 0x40100000 */
|
||||
target_add_ram(t, 0x20000000, 128UL * 1024UL); /* SRAM 128 KB 0x20000000 */
|
||||
target_add_ram(t, 0x1FFE0000, 128UL * 1024UL); /* SRAMHS 128 KB 0x1FFE0000 */
|
||||
target_add_ram(t, 0x200FE000, 8UL * 1024UL); /* Standby SRAM 8 KB 0x200FE000 */
|
||||
break;
|
||||
|
||||
case PNR_SERIES_RA6M2:
|
||||
renesas_add_flash(t, 0x40100000, 32UL * 1024UL, 64); /* Data flash memory 32 KB 0x40100000 */
|
||||
target_add_ram(t, 0x20000000, 256UL * 1024UL); /* SRAM 256 KB 0x20000000 */
|
||||
target_add_ram(t, 0x1FFE0000, 128UL * 1024UL); /* SRAMHS 128 KB 0x1FFE0000 */
|
||||
target_add_ram(t, 0x200FE000, 8UL * 1024UL); /* Standby SRAM 8 KB 0x200FE000 */
|
||||
renesas_add_flash(t, 0x40100000, 32UL * 1024UL); /* Data flash memory 32 KB 0x40100000 */
|
||||
target_add_ram(t, 0x20000000, 256UL * 1024UL); /* SRAM 256 KB 0x20000000 */
|
||||
target_add_ram(t, 0x1FFE0000, 128UL * 1024UL); /* SRAMHS 128 KB 0x1FFE0000 */
|
||||
target_add_ram(t, 0x200FE000, 8UL * 1024UL); /* Standby SRAM 8 KB 0x200FE000 */
|
||||
break;
|
||||
|
||||
case PNR_SERIES_RA6M3:
|
||||
renesas_add_flash(t, 0x40100000, 64UL * 1024UL, 64); /* Data flash memory 64 KB 0x40100000 */
|
||||
target_add_ram(t, 0x20000000, 256UL * 1024UL); /* SRAM0 256 KB 0x20000000 */
|
||||
target_add_ram(t, 0x20040000, 256UL * 1024UL); /* SRAM1 256 KB 0x20040000 */
|
||||
target_add_ram(t, 0x1FFE0000, 128UL * 1024UL); /* SRAMHS 128 KB 0x1FFE0000 */
|
||||
target_add_ram(t, 0x200FE000, 8UL * 1024UL); /* Standby SRAM 8 KB 0x200FE000 */
|
||||
renesas_add_flash(t, 0x40100000, 64UL * 1024UL); /* Data flash memory 64 KB 0x40100000 */
|
||||
target_add_ram(t, 0x20000000, 256UL * 1024UL); /* SRAM0 256 KB 0x20000000 */
|
||||
target_add_ram(t, 0x20040000, 256UL * 1024UL); /* SRAM1 256 KB 0x20040000 */
|
||||
target_add_ram(t, 0x1FFE0000, 128UL * 1024UL); /* SRAMHS 128 KB 0x1FFE0000 */
|
||||
target_add_ram(t, 0x200FE000, 8UL * 1024UL); /* Standby SRAM 8 KB 0x200FE000 */
|
||||
break;
|
||||
|
||||
case PNR_SERIES_RA6M4:
|
||||
case PNR_SERIES_RA6E1:
|
||||
renesas_add_flash(t, 0x08000000, 8UL * 1024UL, 64); /* Data flash memory 8 KB 0x08000000 */
|
||||
target_add_ram(t, 0x20000000, 256UL * 1024UL); /* SRAM 256 KB 0x20000000 */
|
||||
target_add_ram(t, 0x28000000, 1024UL); /* Standby SRAM 1 KB 0x28000000 */
|
||||
renesas_add_flash(t, 0x08000000, 8UL * 1024UL); /* Data flash memory 8 KB 0x08000000 */
|
||||
target_add_ram(t, 0x20000000, 256UL * 1024UL); /* SRAM 256 KB 0x20000000 */
|
||||
target_add_ram(t, 0x28000000, 1024UL); /* Standby SRAM 1 KB 0x28000000 */
|
||||
break;
|
||||
|
||||
case PNR_SERIES_RA6M5:
|
||||
renesas_add_flash(t, 0x08000000, 8UL * 1024UL, 64); /* Data flash memory 8 KB 0x08000000 */
|
||||
target_add_ram(t, 0x20000000, 512UL * 1024UL); /* SRAM 512 KB 0x20000000 */
|
||||
target_add_ram(t, 0x28000000, 1024UL); /* Standby SRAM 1 KB 0x28000000 */
|
||||
renesas_add_flash(t, 0x08000000, 8UL * 1024UL); /* Data flash memory 8 KB 0x08000000 */
|
||||
target_add_ram(t, 0x20000000, 512UL * 1024UL); /* SRAM 512 KB 0x20000000 */
|
||||
target_add_ram(t, 0x28000000, 1024UL); /* Standby SRAM 1 KB 0x28000000 */
|
||||
break;
|
||||
|
||||
case PNR_SERIES_RA6T1:
|
||||
renesas_add_flash(t, 0x40100000, 8UL * 1024UL, 64); /* Data flash memory 8 KB 0x40100000 */
|
||||
target_add_ram(t, 0x1FFE0000, 64UL * 1024UL); /* SRAMHS 64 KB 0x1FFE0000 */
|
||||
renesas_add_flash(t, 0x40100000, 8UL * 1024UL); /* Data flash memory 8 KB 0x40100000 */
|
||||
target_add_ram(t, 0x1FFE0000, 64UL * 1024UL); /* SRAMHS 64 KB 0x1FFE0000 */
|
||||
break;
|
||||
|
||||
case PNR_SERIES_RA6T2:
|
||||
renesas_add_flash(t, 0x08000000, 16UL * 1024UL, 64); /* Data flash memory 16 KB 0x08000000 */
|
||||
target_add_ram(t, 0x20000000, 64UL * 1024UL); /* SRAM 64 KB 0x20000000 */
|
||||
target_add_ram(t, 0x28000000, 1024UL); /* Standby SRAM 1 KB 0x28000000 */
|
||||
renesas_add_flash(t, 0x08000000, 16UL * 1024UL); /* Data flash memory 16 KB 0x08000000 */
|
||||
target_add_ram(t, 0x20000000, 64UL * 1024UL); /* SRAM 64 KB 0x20000000 */
|
||||
target_add_ram(t, 0x28000000, 1024UL); /* Standby SRAM 1 KB 0x28000000 */
|
||||
break;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
renesas_add_flash(t, 0x00000000, renesas_flash_size(pnr), 8UL * 1024UL); /* Code flash memory 0x00000000 */
|
||||
renesas_add_flash(t, 0x00000000, renesas_flash_size(pnr)); /* Code flash memory 0x00000000 */
|
||||
|
||||
target_add_commands(t, renesas_cmd_list, t->driver);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue