We were disabling the UART on all Hardware V1 and newer, as V1 and V2
had the SWD pins connected to the UART pins. Since V3 this is not the
case any more so we can keep the UART enabled when an SWD debugger is
connected to the BMP.
We are using GD32F103 on the BMP V2.3 hardware. The GD32F103 has an
errata for the ADC where the end of conversion (EOC) bit is not reset
when reading the ADC result. This resulted in us not waiting for the new
value to be acquired and reading an old value instead. The solution for
that is resetting the EOC bit manually after reading the ADC result, so
that on the next acquisision we wait for the conversion to finish.
This patch also increases the sampling time as the GD32 have lower ADC
impedance than the STM32 and this should help us read a more accuarate
target voltage.
The BMP with hardware version 4 and newer, use option bytes instead of
physical GPIO to encode the hardware version. In some older BMP there is
a chance that the user option byte is set to 255 (0x00FF pattern). This
can throw off the hardware version detection routine.
The hw rev 4 and 5 both have the version stored in the Data1 user option
byte. This frees up the hw rev strapping pins for other uses, ie swtrace
decoding using USART1 RX, and additional peripherals on the SPI bus,
like bulk flash storage and displays.
Special iRST_SENSE handling does not apply at least for BMP 2.1c.
On V2.1c, iRST_SENSE was set as output high and xRST high shorted
iRST_SENSE to ground via Q2
FIXME: Check for older versions!
This is a questionable fix for the Kinetis K22F that samples
this pin on release from reset to enable its EzPort which
makes the flash unusable and disables the rest of the micro.
1) This version uses a direction control level shifters. We need to control
the direction of the TMS/SWDIO pin.
2.1) Because we want to support a large voltage range for SRST we use an
external dual MOSFET for asserting and sensing the SRST line. We have
added the hardware version 3 to be handled the same way as version 0.
Meaning using separate pins for assertion and sensing of the SRST line.
2.2) The new SRST sense circuit is inverting, thus we have dedicated
code for hardware version 3 that inverts the SRST status pin on read.
BMPM V2 uses a biasing resistor for the true switch mosfet circuit.
Because of that the weak pull-up/down of the stm32 is not asserting the
correct gate voltage for the mosfets to fully switch through. Because of
that we need to use open drain configulation of the GPIO instead.
- Remove connect_assert_srst global.
- Attach functions always release reset.
- Platforms provide a method to poll the reset pin.
- Reset on scan is all internal to command.c
- Reset is released on a failed scan. Fixes#111
If you try to read out the GPIO immediately after setting the weak pull
on the pin it is possible that you will not read the correct value on a
floating pin. We need to use a busy wait loop instead of the
platform_delay because the platform timing is not initialized yet. We
also can not initialize the platform_delay code yet because it requires
LED gpio to be configured. A busy wait seems to do the job and is easier
than refactoring the codebase to use the platform_delay function.
Until now the native hardware was pulling PB5-7 down and checking if
they were asserted high. BMPMV2b is pulling the pins down instead of
high. The hardware version routine now determines the hardware version
based on the fact if a pin is asserted at all. This means that if a pin
is left floating, the version number bit will be 0, and if the pin is
asserted either high or low the bit will be set to 1. While we were
already at it the "monitor version" command in GDB will now also print
the hardware version number.
All source files include general.h first and before anything else.
This inlcludes platform.h and platform_support.h
No header file needs to include to include any of these, but should include
any others needed for it's own declarations.
o Prevent probe from inadvertently powering target. If PWR_BR is
allowed to float, the gate on Q1 (blackmagic_mini) will tend to be
close enough to zero to turn the transistor on. We activate the
internal pull-up on this IO pin to force the transistor off.
USB UART seems to work fine at 115.2Kbps or 230.4Kbps, but starts to drop characters
as the data rate goes higher. This commit changes the usbuart ISR to fill a software
FIFO, and adds a low priority timer interrupt to run deferred processing to drain a
FIFO and send USB CDCACM packets, rather than calling the usb send within the UART
ISR.
Tested on native platform, up to 1.5MBps.
dragonmux
Piotr ESden-Tempski
Rafael Silva
Thiadmer Riemersma
Uwe Bonnes
jxltom
Gareth McMullin
Richard Eoin Meadows
Frantisek Burian
Michael Tharp
Marc Singer
Allen Ibara