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sys64738/r
Author | SHA1 | Date |
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Triss | 780d6daa53 |
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@ -207,10 +207,8 @@ static bool rp_mass_erase(target *t);
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// Our own implementation of bootloader functions for handling flash chip
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// Our own implementation of bootloader functions for handling flash chip
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static void rp_flash_exit_xip(target *const t);
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static void rp_flash_exit_xip(target *const t);
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static void rp_flash_enter_xip(target *const t);
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static void rp_flash_enter_xip(target *const t);
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#if 0
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static void rp_flash_connect_internal(target *const t);
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static void rp_flash_connect_internal(target *const t);
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static void rp_flash_flush_cache(target *const t);
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static void rp_flash_flush_cache(target *const t);
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#endif
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static void rp_spi_read_sfdp(target *const t, const uint32_t address, void *const buffer, const size_t length)
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static void rp_spi_read_sfdp(target *const t, const uint32_t address, void *const buffer, const size_t length)
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{
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{
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@ -225,6 +223,7 @@ static void rp_add_flash(target *t)
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return;
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return;
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}
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}
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rp_flash_connect_internal(t);
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rp_flash_exit_xip(t);
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rp_flash_exit_xip(t);
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spi_parameters_s spi_parameters;
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spi_parameters_s spi_parameters;
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@ -236,6 +235,7 @@ static void rp_add_flash(target *t)
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spi_parameters.sector_erase_opcode = SPI_FLASH_CMD_SECTOR_ERASE;
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spi_parameters.sector_erase_opcode = SPI_FLASH_CMD_SECTOR_ERASE;
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}
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}
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rp_flash_flush_cache(t);
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rp_flash_enter_xip(t);
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rp_flash_enter_xip(t);
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DEBUG_INFO("Flash size: %uMiB\n", spi_parameters.capacity / (1024U * 1024U));
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DEBUG_INFO("Flash size: %uMiB\n", spi_parameters.capacity / (1024U * 1024U));
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@ -621,7 +621,6 @@ static void rp_spi_read(
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target_mem_write32(t, RP_SSI_ENABLE, ssi_enabled);
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target_mem_write32(t, RP_SSI_ENABLE, ssi_enabled);
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}
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}
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#if 0
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// Connect the XIP controller to the flash pads
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// Connect the XIP controller to the flash pads
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static void rp_flash_connect_internal(target *const t)
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static void rp_flash_connect_internal(target *const t)
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{
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{
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@ -643,7 +642,6 @@ static void rp_flash_connect_internal(target *const t)
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target_mem_write32(t, RP_GPIO_QSPI_SD2_CTRL, 0);
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target_mem_write32(t, RP_GPIO_QSPI_SD2_CTRL, 0);
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target_mem_write32(t, RP_GPIO_QSPI_SD3_CTRL, 0);
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target_mem_write32(t, RP_GPIO_QSPI_SD3_CTRL, 0);
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}
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}
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#endif
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// Set up the SSI controller for standard SPI mode,i.e. for every byte sent we get one back
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// Set up the SSI controller for standard SPI mode,i.e. for every byte sent we get one back
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// This is only called by flash_exit_xip(), not by any of the other functions.
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// This is only called by flash_exit_xip(), not by any of the other functions.
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@ -778,7 +776,6 @@ static void rp_flash_exit_xip(target *const t)
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target_mem_write32(t, RP_GPIO_QSPI_CS_CTRL, 0);
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target_mem_write32(t, RP_GPIO_QSPI_CS_CTRL, 0);
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}
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}
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#if 0
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// This is a hook for steps to be taken in between programming the flash and
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// This is a hook for steps to be taken in between programming the flash and
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// doing cached XIP reads from the flash. Called by the bootrom before
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// doing cached XIP reads from the flash. Called by the bootrom before
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// entering flash second stage, and called by the debugger after flash
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// entering flash second stage, and called by the debugger after flash
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@ -793,7 +790,6 @@ static void rp_flash_flush_cache(target *const t)
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target_mem_write32(t, RP_XIP_CTRL, ctrl | RP_XIP_CTRL_ENABLE);
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target_mem_write32(t, RP_XIP_CTRL, ctrl | RP_XIP_CTRL_ENABLE);
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rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_NORMAL);
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rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_NORMAL);
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}
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}
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#endif
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// Put the SSI into a mode where XIP accesses translate to standard
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// Put the SSI into a mode where XIP accesses translate to standard
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// serial 03h read commands. The flash remains in its default serial command
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// serial 03h read commands. The flash remains in its default serial command
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