493 lines
15 KiB
C
493 lines
15 KiB
C
/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2014 Mike Walters <mike@flomp.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements nRF51 target specific functions for detecting
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* the device, providing the XML memory map and Flash memory programming.
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*/
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#include "general.h"
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#include "target.h"
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#include "target_internal.h"
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#include "cortexm.h"
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#include "adiv5.h"
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static int nrf51_flash_erase(target_flash_s *f, target_addr_t addr, size_t len);
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static int nrf51_flash_write(target_flash_s *f, target_addr_t dest, const void *src, size_t len);
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static bool nrf51_mass_erase(target *t);
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static bool nrf51_cmd_erase_uicr(target *t, int argc, const char **argv);
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static bool nrf51_cmd_protect_flash(target *t, int argc, const char **argv);
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static bool nrf51_cmd_read_hwid(target *t, int argc, const char **argv);
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static bool nrf51_cmd_read_fwid(target *t, int argc, const char **argv);
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static bool nrf51_cmd_read_deviceid(target *t, int argc, const char **argv);
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static bool nrf51_cmd_read_deviceaddr(target *t, int argc, const char **argv);
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static bool nrf51_cmd_read_deviceinfo(target *t, int argc, const char **argv);
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static bool nrf51_cmd_read_help(target *t, int argc, const char **argv);
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static bool nrf51_cmd_read(target *t, int argc, const char **argv);
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const struct command_s nrf51_cmd_list[] = {
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{"erase_uicr", (cmd_handler)nrf51_cmd_erase_uicr, "Erase UICR registers"},
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{"protect_flash", (cmd_handler)nrf51_cmd_protect_flash, "Enable flash read/write protection"},
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{"read", (cmd_handler)nrf51_cmd_read, "Read device parameters"},
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{NULL, NULL, NULL}
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};
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const struct command_s nrf51_read_cmd_list[] = {
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{"help", (cmd_handler)nrf51_cmd_read_help, "Display help for read commands"},
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{"hwid", (cmd_handler)nrf51_cmd_read_hwid, "Read hardware identification number"},
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{"fwid", (cmd_handler)nrf51_cmd_read_fwid, "Read pre-loaded firmware ID"},
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{"deviceid", (cmd_handler)nrf51_cmd_read_deviceid, "Read unique device ID"},
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{"deviceaddr", (cmd_handler)nrf51_cmd_read_deviceaddr, "Read device address"},
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{"deviceinfo", (cmd_handler)nrf51_cmd_read_deviceinfo, "Read device information"},
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{NULL, NULL, NULL}
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};
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/* Non-Volatile Memory Controller (NVMC) Registers */
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#define NRF51_NVMC 0x4001E000
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#define NRF51_NVMC_READY (NRF51_NVMC + 0x400)
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#define NRF51_NVMC_CONFIG (NRF51_NVMC + 0x504)
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#define NRF51_NVMC_ERASEPAGE (NRF51_NVMC + 0x508)
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#define NRF51_NVMC_ERASEALL (NRF51_NVMC + 0x50C)
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#define NRF51_NVMC_ERASEUICR (NRF51_NVMC + 0x514)
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#define NRF51_NVMC_CONFIG_REN 0x0 // Read only access
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#define NRF51_NVMC_CONFIG_WEN 0x1 // Write enable
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#define NRF51_NVMC_CONFIG_EEN 0x2 // Erase enable
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/* Factory Information Configuration Registers (FICR) */
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#define NRF51_FICR 0x10000000
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#define NRF51_FICR_CODEPAGESIZE (NRF51_FICR + 0x010)
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#define NRF51_FICR_CODESIZE (NRF51_FICR + 0x014)
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#define NRF51_FICR_CONFIGID (NRF51_FICR + 0x05C)
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#define NRF51_FICR_DEVICEID_LOW (NRF51_FICR + 0x060)
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#define NRF51_FICR_DEVICEID_HIGH (NRF51_FICR + 0x064)
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#define NRF51_FICR_DEVICEADDRTYPE (NRF51_FICR + 0x0A0)
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#define NRF51_FICR_DEVICEADDR_LOW (NRF51_FICR + 0x0A4)
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#define NRF51_FICR_DEVICEADDR_HIGH (NRF51_FICR + 0x0A8)
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#define NRF52_PART_INFO (NRF51_FICR + 0x100)
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#define NRF52_INFO_RAM (NRF51_FICR + 0x10C)
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/* Device Info Registers */
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#define NRF51_FICR_DEVICE_INFO_BASE (NRF51_FICR + 0x100)
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#define NRF51_FICR_DEVICE_INFO_PART NRF51_FICR_DEVICE_INFO_BASE
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#define NRF51_FICR_DEVICE_INFO_VARIANT (NRF51_FICR_DEVICE_INFO_BASE + 4)
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#define NRF51_FICR_DEVICE_INFO_PACKAGE (NRF51_FICR_DEVICE_INFO_BASE + 8)
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#define NRF51_FICR_DEVICE_INFO_RAM (NRF51_FICR_DEVICE_INFO_BASE + 12)
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#define NRF51_FICR_DEVICE_INFO_FLASH (NRF51_FICR_DEVICE_INFO_BASE + 16)
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#define NRF51_FIELD_UNSPECIFIED (0xFFFFFFFF)
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/* User Information Configuration Registers (UICR) */
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#define NRF51_UICR 0x10001000
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/* Flash R/W Protection Register */
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#define NRF51_APPROTECT 0x10001208
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#define NRF51_PAGE_SIZE 1024
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#define NRF52_PAGE_SIZE 4096
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static void nrf51_add_flash(target *t,
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uint32_t addr, size_t length, size_t erasesize)
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{
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target_flash_s *f = calloc(1, sizeof(*f));
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if (!f) { /* calloc failed: heap exhaustion */
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DEBUG_WARN("calloc: failed in %s\n", __func__);
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return;
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}
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f->start = addr;
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f->length = length;
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f->blocksize = erasesize;
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f->erase = nrf51_flash_erase;
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f->write = nrf51_flash_write;
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f->erased = 0xff;
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target_add_flash(t, f);
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}
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bool nrf51_probe(target *t)
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{
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uint32_t page_size = target_mem_read32(t, NRF51_FICR_CODEPAGESIZE);
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uint32_t code_size = target_mem_read32(t, NRF51_FICR_CODESIZE);
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/* Check that page_size and code_size makes sense */
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if ((page_size == 0xffffffff) || (code_size == 0xffffffff) ||
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(page_size == 0) || (code_size == 0) ||
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(page_size > 0x10000) || (code_size > 0x10000))
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return false;
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/* Check that device identifier makes sense */
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uint32_t uid0 = target_mem_read32(t, NRF51_FICR_DEVICEID_LOW);
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uint32_t uid1 = target_mem_read32(t, NRF51_FICR_DEVICEID_HIGH);
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if ((uid0 == 0xffffffff) || (uid1 == 0xffffffff) ||
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(uid0 == 0) || (uid1 == 0))
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return false;
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t->mass_erase = nrf51_mass_erase;
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/* Test for NRF52 device*/
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uint32_t info_part = target_mem_read32(t, NRF52_PART_INFO);
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if ((info_part != 0xffffffff) && (info_part != 0) &&
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((info_part & 0x00ff000) == 0x52000)) {
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uint32_t ram_size = target_mem_read32(t, NRF52_INFO_RAM);
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t->driver = "Nordic nRF52";
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t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
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target_add_ram(t, 0x20000000, ram_size * 1024);
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nrf51_add_flash(t, 0, page_size * code_size, page_size);
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nrf51_add_flash(t, NRF51_UICR, page_size, page_size);
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target_add_commands(t, nrf51_cmd_list, "nRF52");
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} else {
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t->driver = "Nordic nRF51";
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/* Use the biggest RAM size seen in NRF51 fammily.
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* IDCODE is kept as '0', as deciphering is hard and
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* there is later no usage.*/
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target_add_ram(t, 0x20000000, 0x8000);
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t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
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nrf51_add_flash(t, 0, page_size * code_size, page_size);
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nrf51_add_flash(t, NRF51_UICR, page_size, page_size);
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target_add_commands(t, nrf51_cmd_list, "nRF51");
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}
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return true;
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}
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static int nrf51_flash_erase(target_flash_s *f, target_addr_t addr, size_t len)
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{
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target *t = f->t;
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/* Enable erase */
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target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
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if(target_check_error(t))
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return -1;
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while (len) {
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if (addr == NRF51_UICR) // Special Case
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/* Write to the ERASE_UICR register to erase */
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target_mem_write32(t, NRF51_NVMC_ERASEUICR, 0x1);
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else // Standard Flash Page
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/* Write address of first word in page to erase it */
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target_mem_write32(t, NRF51_NVMC_ERASEPAGE, addr);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0) {
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if (target_check_error(t))
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return -1;
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}
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addr += f->blocksize;
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if (len > f->blocksize)
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len -= f->blocksize;
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else
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len = 0;
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}
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/* Return to read-only */
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target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0) {
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if (target_check_error(t))
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return -1;
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}
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return 0;
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}
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static int nrf51_flash_write(target_flash_s *f, target_addr_t dest, const void *src, size_t len)
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{
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target *t = f->t;
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/* Enable write */
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target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_WEN);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
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if(target_check_error(t))
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return -1;
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target_mem_write(t, dest, src, len);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
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if(target_check_error(t))
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return -1;
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/* Return to read-only */
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target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN);
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return 0;
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}
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static bool nrf51_mass_erase(target *t)
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{
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target_reset(t);
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/* Enable erase */
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target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0) {
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if (target_check_error(t))
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return false;
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}
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platform_timeout timeout = {};
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platform_timeout_set(&timeout, 500);
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/* Erase all */
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target_mem_write32(t, NRF51_NVMC_ERASEALL, 1);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0) {
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if (target_check_error(t))
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return false;
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target_print_progress(&timeout);
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}
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return true;
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}
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static bool nrf51_cmd_erase_uicr(target *t, int argc, const char **argv)
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{
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(void)argc;
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(void)argv;
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tc_printf(t, "erase..\n");
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/* Enable erase */
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target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
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if(target_check_error(t))
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return false;
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/* Erase UICR */
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target_mem_write32(t, NRF51_NVMC_ERASEUICR, 1);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
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if(target_check_error(t))
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return false;
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return true;
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}
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static bool nrf51_cmd_protect_flash(target *t, int argc, const char **argv)
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{
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(void)argc;
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(void)argv;
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tc_printf(t, "protect flash..\n");
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/* Enable write */
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target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_WEN);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0) {
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if(target_check_error(t))
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return false;
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}
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target_mem_write32(t, NRF51_APPROTECT, 0xFFFFFF00);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0) {
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if(target_check_error(t))
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return false;
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}
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return true;
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}
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static bool nrf51_cmd_read_hwid(target *t, int argc, const char **argv)
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{
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(void)argc;
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(void)argv;
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uint32_t hwid = target_mem_read32(t, NRF51_FICR_CONFIGID) & 0xFFFF;
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tc_printf(t, "Hardware ID: 0x%04X\n", hwid);
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return true;
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}
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static bool nrf51_cmd_read_fwid(target *t, int argc, const char **argv)
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{
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(void)argc;
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(void)argv;
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uint32_t fwid = (target_mem_read32(t, NRF51_FICR_CONFIGID) >> 16) & 0xFFFF;
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tc_printf(t, "Firmware ID: 0x%04X\n", fwid);
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return true;
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}
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static bool nrf51_cmd_read_deviceid(target *t, int argc, const char **argv)
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{
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(void)argc;
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(void)argv;
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uint32_t deviceid_low = target_mem_read32(t, NRF51_FICR_DEVICEID_LOW);
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uint32_t deviceid_high = target_mem_read32(t, NRF51_FICR_DEVICEID_HIGH);
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tc_printf(t, "Device ID: 0x%08X%08X\n", deviceid_high, deviceid_low);
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return true;
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}
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static bool nrf51_cmd_read_deviceinfo(target *t, int argc, const char **argv)
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{
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(void)argc;
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(void)argv;
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struct deviceinfo{
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uint32_t part;
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union{
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char c[4];
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uint32_t f;
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} variant;
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uint32_t package;
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uint32_t ram;
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uint32_t flash;
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} di;
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di.package = target_mem_read32(t, NRF51_FICR_DEVICE_INFO_PACKAGE);
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di.part = target_mem_read32(t, NRF51_FICR_DEVICE_INFO_PART);
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di.ram = target_mem_read32(t, NRF51_FICR_DEVICE_INFO_RAM);
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di.flash = target_mem_read32(t, NRF51_FICR_DEVICE_INFO_FLASH);
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di.variant.f = target_mem_read32(t, NRF51_FICR_DEVICE_INFO_VARIANT);
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tc_printf(t, "Part:\t\tNRF%X\n",di.part);
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tc_printf(t, "Variant:\t%c%c%c%c\n",
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di.variant.c[3],
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di.variant.c[2],
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di.variant.c[1],
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di.variant.c[0]);
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tc_printf(t, "Package:\t");
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switch (di.package)
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{
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case NRF51_FIELD_UNSPECIFIED:
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tc_printf(t,"Unspecified\n");
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break;
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case 0x2000:
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tc_printf(t,"QF\n");
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break;
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case 0x2001:
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tc_printf(t,"CI\n");
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break;
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case 0x2004:
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tc_printf(t,"QIxx\n");
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break;
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default:
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tc_printf(t,"Unknown (Code %X)\n",di.package);
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break;
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}
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tc_printf(t, "Ram:\t\t%uK\n", di.ram);
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tc_printf(t, "Flash:\t\t%uK\n", di.flash);
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return true;
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}
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static bool nrf51_cmd_read_deviceaddr(target *t, int argc, const char **argv)
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{
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(void)argc;
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(void)argv;
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uint32_t addr_type = target_mem_read32(t, NRF51_FICR_DEVICEADDRTYPE);
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uint32_t addr_low = target_mem_read32(t, NRF51_FICR_DEVICEADDR_LOW);
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uint32_t addr_high = target_mem_read32(t, NRF51_FICR_DEVICEADDR_HIGH) & 0xFFFF;
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if ((addr_type & 1) == 0) {
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tc_printf(t, "Publicly Listed Address: 0x%04X%08X\n", addr_high, addr_low);
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} else {
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tc_printf(t, "Randomly Assigned Address: 0x%04X%08X\n", addr_high, addr_low);
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}
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return true;
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}
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static bool nrf51_cmd_read_help(target *t, int argc, const char **argv)
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{
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(void)argc;
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(void)argv;
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const struct command_s *c;
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tc_printf(t, "Read commands:\n");
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for(c = nrf51_read_cmd_list; c->cmd; c++)
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tc_printf(t, "\t%s -- %s\n", c->cmd, c->help);
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return true;
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}
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static bool nrf51_cmd_read(target *t, int argc, const char **argv)
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{
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const struct command_s *c;
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if (argc > 1) {
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for(c = nrf51_read_cmd_list; c->cmd; c++) {
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/* Accept a partial match as GDB does.
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* So 'mon ver' will match 'monitor version'
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*/
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if(!strncmp(argv[1], c->cmd, strlen(argv[1])))
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return !c->handler(t, argc - 1, &argv[1]);
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}
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}
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return nrf51_cmd_read_help(t, 0, NULL);
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}
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#define NRF52_MDM_IDR 0x02880000
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static bool nrf51_mdm_mass_erase(target *t);
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#define MDM_POWER_EN ADIV5_DP_REG(0x01)
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#define MDM_SELECT_AP ADIV5_DP_REG(0x02)
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#define MDM_STATUS ADIV5_AP_REG(0x08)
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#define MDM_CONTROL ADIV5_AP_REG(0x04)
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#define MDM_PROT_EN ADIV5_AP_REG(0x0C)
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bool nrf51_mdm_probe(ADIv5_AP_t *ap)
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{
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switch(ap->idr) {
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case NRF52_MDM_IDR:
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break;
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default:
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return false;
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}
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target *t = target_new();
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if (!t) {
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return false;
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}
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t->mass_erase = nrf51_mdm_mass_erase;
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adiv5_ap_ref(ap);
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t->priv = ap;
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t->priv_free = (void*)adiv5_ap_unref;
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uint32_t status = adiv5_ap_read(ap, MDM_PROT_EN);
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status = adiv5_ap_read(ap, MDM_PROT_EN);
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if (status)
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t->driver = "Nordic nRF52 Access Port";
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else
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t->driver = "Nordic nRF52 Access Port (protected)";
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t->regs_size = 4;
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return true;
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}
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static bool nrf51_mdm_mass_erase(target *t)
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{
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ADIv5_AP_t *ap = t->priv;
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uint32_t status = adiv5_ap_read(ap, MDM_STATUS);
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adiv5_dp_write(ap->dp, MDM_POWER_EN, 0x50000000);
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adiv5_dp_write(ap->dp, MDM_SELECT_AP, 0x01000000);
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adiv5_ap_write(ap, MDM_CONTROL, 0x00000001);
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platform_timeout timeout;
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platform_timeout_set(&timeout, 500);
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// Read until 0, probably should have a timeout here...
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do {
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status = adiv5_ap_read(ap, MDM_STATUS);
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target_print_progress(&timeout);
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} while (status);
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// The second read will provide true prot status
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status = adiv5_ap_read(ap, MDM_PROT_EN);
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status = adiv5_ap_read(ap, MDM_PROT_EN);
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// should we return the prot status here?
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return true;
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}
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