197 lines
7.2 KiB
C
197 lines
7.2 KiB
C
/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2015 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TARGET_CORTEXM_H
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#define TARGET_CORTEXM_H
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#include "target.h"
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#include "adiv5.h"
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extern unsigned cortexm_wait_timeout;
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/* Private peripheral bus base address */
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#define CORTEXM_PPB_BASE 0xe0000000U
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#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xe000U)
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#define CORTEXM_CPUID (CORTEXM_SCS_BASE + 0xd00U)
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#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xd0cU)
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#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xd28U)
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#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xd2cU)
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#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xd30U)
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#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xd88U)
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#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xdf0U)
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#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xdf4U)
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#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xdf8U)
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#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xdfcU)
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/* Cache identification */
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#define CORTEXM_CLIDR (CORTEXM_SCS_BASE + 0xd78U)
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#define CORTEXM_CTR (CORTEXM_SCS_BASE + 0xd7cU)
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#define CORTEXM_CCSIDR (CORTEXM_SCS_BASE + 0xd80U)
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#define CORTEXM_CSSELR (CORTEXM_SCS_BASE + 0xd84U)
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/* Cache maintenance operations */
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#define CORTEXM_ICIALLU (CORTEXM_SCS_BASE + 0xf50U)
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#define CORTEXM_DCCMVAC (CORTEXM_SCS_BASE + 0xf68U)
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#define CORTEXM_DCCIMVAC (CORTEXM_SCS_BASE + 0xf70U)
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#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000U)
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/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */
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#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000U)
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#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004U)
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#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008U + (4U * (i)))
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#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000U)
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#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000U)
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#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020U + (0x10U * (i)))
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#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024U + (0x10U * (i)))
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#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028U + (0x10U * (i)))
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/* Application Interrupt and Reset Control Register (AIRCR) */
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#define CORTEXM_AIRCR_VECTKEY (0x05faU << 16U)
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/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */
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#define CORTEXM_AIRCR_ENDIANESS (1U << 15U)
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/* Bits 15:11 - Unused, reserved */
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#define CORTEXM_AIRCR_PRIGROUP (7U << 8U)
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/* Bits 7:3 - Unused, reserved */
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#define CORTEXM_AIRCR_SYSRESETREQ (1U << 2U)
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#define CORTEXM_AIRCR_VECTCLRACTIVE (1U << 1U)
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#define CORTEXM_AIRCR_VECTRESET (1U << 0U)
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/* HardFault Status Register (HFSR) */
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#define CORTEXM_HFSR_DEBUGEVT (1U << 31U)
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#define CORTEXM_HFSR_FORCED (1U << 30U)
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/* Bits 29:2 - Not specified */
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#define CORTEXM_HFSR_VECTTBL (1U << 1U)
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/* Bits 0 - Reserved */
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/* Debug Fault Status Register (DFSR) */
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/* Bits 31:5 - Reserved */
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#define CORTEXM_DFSR_RESETALL 0x1fU
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#define CORTEXM_DFSR_EXTERNAL (1U << 4U)
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#define CORTEXM_DFSR_VCATCH (1U << 3U)
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#define CORTEXM_DFSR_DWTTRAP (1U << 2U)
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#define CORTEXM_DFSR_BKPT (1U << 1U)
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#define CORTEXM_DFSR_HALTED (1U << 0U)
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/* Debug Halting Control and Status Register (DHCSR) */
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/* This key must be written to bits 31:16 for write to take effect */
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#define CORTEXM_DHCSR_DBGKEY 0xa05f0000U
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/* Bits 31:26 - Reserved */
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#define CORTEXM_DHCSR_S_RESET_ST (1U << 25U)
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#define CORTEXM_DHCSR_S_RETIRE_ST (1U << 24U)
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/* Bits 23:20 - Reserved */
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#define CORTEXM_DHCSR_S_LOCKUP (1U << 19U)
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#define CORTEXM_DHCSR_S_SLEEP (1U << 18U)
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#define CORTEXM_DHCSR_S_HALT (1U << 17U)
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#define CORTEXM_DHCSR_S_REGRDY (1U << 16U)
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/* Bits 15:6 - Reserved */
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#define CORTEXM_DHCSR_C_SNAPSTALL (1U << 5U) /* v7m only */
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/* Bit 4 - Reserved */
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#define CORTEXM_DHCSR_C_MASKINTS (1U << 3U)
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#define CORTEXM_DHCSR_C_STEP (1U << 2U)
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#define CORTEXM_DHCSR_C_HALT (1U << 1U)
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#define CORTEXM_DHCSR_C_DEBUGEN (1U << 0U)
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/* Debug Core Register Selector Register (DCRSR) */
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#define CORTEXM_DCRSR_REGWnR 0x00010000
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#define CORTEXM_DCRSR_REGSEL_MASK 0x0000001f
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#define CORTEXM_DCRSR_REGSEL_XPSR 0x00000010
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#define CORTEXM_DCRSR_REGSEL_MSP 0x00000011
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#define CORTEXM_DCRSR_REGSEL_PSP 0x00000012
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/* Debug Exception and Monitor Control Register (DEMCR) */
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/* Bits 31:25 - Reserved */
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#define CORTEXM_DEMCR_TRCENA (1U << 24U)
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/* Bits 23:20 - Reserved */
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#define CORTEXM_DEMCR_MON_REQ (1U << 19U) /* v7m only */
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#define CORTEXM_DEMCR_MON_STEP (1U << 18U) /* v7m only */
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#define CORTEXM_DEMCR_VC_MON_PEND (1U << 17U) /* v7m only */
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#define CORTEXM_DEMCR_VC_MON_EN (1U << 16U) /* v7m only */
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/* Bits 15:11 - Reserved */
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#define CORTEXM_DEMCR_VC_HARDERR (1U << 10U)
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#define CORTEXM_DEMCR_VC_INTERR (1U << 9U) /* v7m only */
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#define CORTEXM_DEMCR_VC_BUSERR (1U << 8U) /* v7m only */
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#define CORTEXM_DEMCR_VC_STATERR (1U << 7U) /* v7m only */
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#define CORTEXM_DEMCR_VC_CHKERR (1U << 6U) /* v7m only */
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#define CORTEXM_DEMCR_VC_NOCPERR (1U << 5U) /* v7m only */
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#define CORTEXM_DEMCR_VC_MMERR (1U << 4U) /* v7m only */
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/* Bits 3:1 - Reserved */
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#define CORTEXM_DEMCR_VC_CORERESET (1U << 0U)
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/* Flash Patch and Breakpoint Control Register (FP_CTRL) */
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/* Bits 32:15 - Reserved */
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/* Bits 14:12 - NUM_CODE2 */ /* v7m only */
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/* Bits 11:8 - NUM_LIT */ /* v7m only */
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/* Bits 7:4 - NUM_CODE1 */
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/* Bits 3:2 - Unspecified */
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#define CORTEXM_FPB_CTRL_KEY (1U << 1U)
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#define CORTEXM_FPB_CTRL_ENABLE (1U << 0U)
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/* Data Watchpoint and Trace Mask Register (DWT_MASKx)
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* The value here is the number of address bits we mask out */
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#define CORTEXM_DWT_MASK_BYTE (0U)
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#define CORTEXM_DWT_MASK_HALFWORD (1U)
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#define CORTEXM_DWT_MASK_WORD (2U)
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#define CORTEXM_DWT_MASK_DWORD (3U)
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/* Data Watchpoint and Trace Function Register (DWT_FUNCTIONx) */
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#define CORTEXM_DWT_FUNC_MATCHED (1U << 24U)
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#define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2U << 10U) /* v7m only */
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#define CORTEXM_DWT_FUNC_FUNC_READ (5U << 0U)
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#define CORTEXM_DWT_FUNC_FUNC_WRITE (6U << 0U)
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#define CORTEXM_DWT_FUNC_FUNC_ACCESS (7U << 0U)
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#define REG_SP 13U
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#define REG_LR 14U
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#define REG_PC 15U
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#define REG_XPSR 16U
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#define REG_MSP 17U
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#define REG_PSP 18U
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#define REG_SPECIAL 19U
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#define ARM_THUMB_BREAKPOINT 0xbe00U
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#define CORTEXM_XPSR_THUMB (1U << 24U)
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#define CORTEXM_TOPT_INHIBIT_NRST (1U << 2U)
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enum cortexm_types {
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CORTEX_M0 = 0xc200,
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CORTEX_M0P = 0xc600,
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CORTEX_M3 = 0xc230,
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CORTEX_M4 = 0xc240,
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CORTEX_M7 = 0xc270,
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CORTEX_M23 = 0xd200,
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CORTEX_M33 = 0xd210,
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};
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#define CPUID_PARTNO_MASK 0xfff0U
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#define CPUID_REVISION_MASK 0x00f00000U
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#define CPUID_PATCH_MASK 0xfU
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ADIv5_AP_t *cortexm_ap(target *t);
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bool cortexm_attach(target *t);
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void cortexm_detach(target *t);
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int cortexm_run_stub(target *t, uint32_t loadaddr, uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
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int cortexm_mem_write_sized(target *t, target_addr_t dest, const void *src, size_t len, enum align align);
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#endif /* TARGET_CORTEXM_H */
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