140 lines
4.0 KiB
C
140 lines
4.0 KiB
C
/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2011 Black Sphere Technologies Ltd.
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* Written by Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements TI/LMI LM3S target specific functions providing
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* the XML memory map and Flash memory programming.
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*
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* According to: TivaTM TM4C123GH6PM Microcontroller Datasheet
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*/
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#include "general.h"
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#include "target.h"
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#include "target_internal.h"
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#include "cortexm.h"
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#define SRAM_BASE 0x20000000
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#define STUB_BUFFER_BASE ALIGN(SRAM_BASE + sizeof(lmi_flash_write_stub), 4)
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#define BLOCK_SIZE 0x400
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#define LMI_SCB_BASE 0x400FE000
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#define LMI_SCB_DID1 (LMI_SCB_BASE + 0x004)
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#define LMI_FLASH_BASE 0x400FD000
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#define LMI_FLASH_FMA (LMI_FLASH_BASE + 0x000)
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#define LMI_FLASH_FMC (LMI_FLASH_BASE + 0x008)
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#define LMI_FLASH_FMC_WRITE (1 << 0)
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#define LMI_FLASH_FMC_ERASE (1 << 1)
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#define LMI_FLASH_FMC_MERASE (1 << 2)
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#define LMI_FLASH_FMC_COMT (1 << 3)
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#define LMI_FLASH_FMC_WRKEY 0xA4420000
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static int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len);
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static int lmi_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len);
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static const char lmi_driver_str[] = "TI Stellaris/Tiva";
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static const uint16_t lmi_flash_write_stub[] = {
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#include "flashstub/lmi.stub"
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};
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static void lmi_add_flash(target *t, size_t length)
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{
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struct target_flash *f = calloc(1, sizeof(*f));
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f->start = 0;
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f->length = length;
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f->blocksize = 0x400;
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f->erase = lmi_flash_erase;
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f->write = lmi_flash_write;
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f->erased = 0xff;
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target_add_flash(t, f);
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}
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bool lmi_probe(target *t)
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{
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uint32_t did1 = target_mem_read32(t, LMI_SCB_DID1);
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switch (did1 >> 16) {
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case 0x1049: /* LM3S3748 */
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t->driver = lmi_driver_str;
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target_add_ram(t, 0x20000000, 0x8000);
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lmi_add_flash(t, 0x40000);
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return true;
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case 0x10A1: /* TM4C123GH6PM */
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t->driver = lmi_driver_str;
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target_add_ram(t, 0x20000000, 0x10000);
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lmi_add_flash(t, 0x80000);
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/* On Tiva targets, asserting SRST results in the debug
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* logic also being reset. We can't assert SRST and must
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* only use the AIRCR SYSRESETREQ. */
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t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
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return true;
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case 0x1022: /* TM4C1230C3PM */
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t->driver = lmi_driver_str;
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target_add_ram(t, 0x20000000, 0x6000);
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lmi_add_flash(t, 0x10000);
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t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
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return true;
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}
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return false;
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}
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int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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{
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target *t = f->t;
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target_check_error(t);
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while(len) {
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target_mem_write32(t, LMI_FLASH_FMA, addr);
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target_mem_write32(t, LMI_FLASH_FMC,
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LMI_FLASH_FMC_WRKEY | LMI_FLASH_FMC_ERASE);
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while (target_mem_read32(t, LMI_FLASH_FMC) &
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LMI_FLASH_FMC_ERASE);
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if (target_check_error(t))
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return -1;
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len -= BLOCK_SIZE;
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addr += BLOCK_SIZE;
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}
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return 0;
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}
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int lmi_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len)
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{
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target *t = f->t;
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target_check_error(t);
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target_mem_write(t, SRAM_BASE, lmi_flash_write_stub,
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sizeof(lmi_flash_write_stub));
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target_mem_write(t, STUB_BUFFER_BASE, src, len);
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if (target_check_error(t))
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return -1;
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return cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, 0);
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}
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