dragonzap/glitcher-r21.kicad_pcb

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2022-01-18 00:32:04 +00:00
(kicad_pcb (version 20211014) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
)
(setup
(pad_to_mask_clearance 0)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(svguseinch false)
(svgprecision 6)
(excludeedgelayer true)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory "dragonzap/gerber/")
)
)
(net 0 "")
(net 1 "GND")
(net 2 "VBUS")
(net 3 "+3V3")
(net 4 "+3.3VADC")
(net 5 "Net-(D100-Pad1)")
(net 6 "UART_RX")
(net 7 "UART_TX")
(net 8 "/controller/SWDIO")
(net 9 "/controller/SWCLK")
(net 10 "Net-(J102-Pad6)")
(net 11 "Net-(J102-Pad7)")
(net 12 "Net-(J102-Pad8)")
(net 13 "GPIO_P0D")
(net 14 "GPIO_P0W")
(net 15 "GPIO_P1D")
(net 16 "GPIO_P1W")
(net 17 "TRIG_IN")
(net 18 "GLITCH_OUT")
(net 19 "P22PWM")
(net 20 "ADC0")
(net 21 "ADC1")
(net 22 "Net-(U100-Pad34)")
(net 23 "Net-(U100-Pad39)")
(net 24 "GPIO_S3W")
(net 25 "GPIO_S3D")
(net 26 "GPIO_S2W")
(net 27 "GPIO_S2D")
(net 28 "GPIO_S1W")
(net 29 "GPIO_S1D")
(net 30 "GPIO_S0W")
(net 31 "GPIO_S0D")
(net 32 "DPOT_DAT")
(net 33 "DPOT_CLK")
(net 34 "Net-(U100-Pad7)")
(net 35 "MAX_SW_B")
(net 36 "MAX_SW_A")
(net 37 "MAX_EN")
(net 38 "DPOT_HI")
(net 39 "Net-(C400-Pad1)")
(net 40 "Net-(D300-Pad1)")
(net 41 "Vdcflt")
(net 42 "Vdclo")
(net 43 "GLITCH_SIG")
(net 44 "DPOT_W")
(net 45 "/glitchout/Vglitch_lo")
(net 46 "DPOT_LO")
(net 47 "Net-(U100-Pad30)")
(net 48 "Net-(JP400-Pad4)")
(net 49 "Net-(JP300-Pad2)")
(net 50 "Net-(C302-Pad1)")
(net 51 "Net-(C305-Pad1)")
(net 52 "EMERG_SHDN")
(net 53 "~{EMERG_SHDN}")
(net 54 "Net-(U401-Pad13)")
(net 55 "Net-(U302-Pad4)")
(net 56 "Net-(U302-Pad7)")
(net 57 "Net-(U302-Pad6)")
(net 58 "Net-(R403-Pad1)")
(net 59 "Net-(J500-Pad1)")
(net 60 "/glitchout/Vdclo_def")
(footprint "Diode_SMD:D_SOD-123" (layer "F.Cu")
(tedit 58645DC7) (tstamp 00000000-0000-0000-0000-000061c2e5ee)
(at 135.128 80.899)
(descr "SOD-123")
(tags "SOD-123")
(path "/00000000-0000-0000-0000-000061ca9896/00000000-0000-0000-0000-000062502c0f")
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(tedit 58645DC7) (tstamp 00000000-0000-0000-0000-000061c41eab)
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(tedit 58645DC7) (tstamp 00000000-0000-0000-0000-000061c44357)
(at 192.913 104.013)
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(gr_text "Custom hi voltage has\n4 sources, picked using\nJP300:\n* PWM on Pico pin 22\n* WPM404 buck-boost\n converter module\n* Buck-boost converter (U301 etc)\n* LDO converter using (U302 etc)\nEverything except the WPM404 can be\ncontrolled by the Pico (PWM/digipot).\n An optional LPF is available to remove\n ripple on the line. You want this for all\n sources except the LDO.\n The high and low values can be\n read back using the Pico ADCs\n for digital feedback control.\n Tune the WPM404 using a DMM." (at 129.794 114.808) (layer "B.SilkS") (tstamp eacb8113-e0ce-4580-bfb3-1a131027d34b)
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(gr_text "or connect bottom pin\nto bench power supply" (at 150.622 93.472) (layer "F.SilkS") (tstamp 6c6c213f-0125-4841-a04e-5210f411774b)
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(gr_text "Short these\ntwo if U400\nnot placed" (at 149.733 82.804) (layer "F.SilkS") (tstamp abee0a2f-9fba-43ed-bd4f-03e3c80e7647)
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(gr_text "only place one\nof PSU C,D or\ndigipot control\nwill go bad" (at 105.283 88.773) (layer "F.SilkS") (tstamp ba546f3f-9f91-45b7-b7e2-ee37445d0461)
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(gr_text "or connect right pin to\nbench power supply" (at 161.671 79.502) (layer "F.SilkS") (tstamp bce5b1ac-044e-4b74-9db6-acb90b2d00f2)
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(gr_text "P0 P1 S3 S2 S1 S0" (at 195.326 110.236 -90) (layer "F.SilkS") (tstamp ce5a0737-4574-43c4-8820-2d26c3912c9e)
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(gr_text "Glitching frontend" (at 186.69 85.344 90) (layer "F.SilkS") (tstamp f6f1d552-75bb-4b55-b8a4-e2bf105fbebb)
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(gr_text "GLITCH OUT" (at 193.421 80.518 90) (layer "F.SilkS") (tstamp ff8c2871-7c9b-4de3-baec-30db09fd1a6f)
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(gr_text "TODO:\n* ~{EMERG}: long line -> can pick up noise -> add small cap for filtering?\n\nnotes:\n* not caring about crosstalk all that much for trig/glitch lines, theyre\n far away from USB, PWM and GPIO, the rest (eg. digipot I2C) is only\n active while not actively glitching. so the only relevant parasitics\n here are capacitances and inductances. not placing the ground plane\n under the two lines should hopefully help a bit here" (at 119.761 45.212) (layer "Dwgs.User") (tstamp 05f67689-b87d-4a73-ba19-8cfc59729f07)
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(gr_text "107.4420 mm" (at 148.082 58.159) (layer "Dwgs.User") (tstamp 2e44eb9d-5214-4281-b589-6f1d5d809dae)
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(gr_text "64.2620 mm" (at 89.401 96.774 90) (layer "Dwgs.User") (tstamp bbb56580-aa81-45cb-b1b7-ba0c984ed065)
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