v1, targetting vdd

2021-12-22 04:52:35 +01:00 · 2021-12-22 04:52:35 +01:00 · d51f1f36e6
commit d51f1f36e6
4 changed files with 632 additions and 0 deletions
--- a/.gitignore
+++ b/.gitignore
@ -0,0 +1,3 @@
+*-cache*
+sym-lib-table
+*-bak
--- a/glitcher.kicad_pcb
+++ b/glitcher.kicad_pcb
@ -0,0 +1 @@
+(kicad_pcb (version 4) (host kicad "dummy file") )
--- a/glitcher.pro
+++ b/glitcher.pro
@ -0,0 +1,43 @@
+update=ma 06 dec 2021 23:35:12
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
--- a/glitcher.sch
+++ b/glitcher.sch
@ -0,0 +1,585 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
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+Date ""
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+F 3 "https://www.renesas.com/us/en/document/dst/rl78g11-datasheet-rev240?language=en&r=1054276" H 7100 4050 50  0001 C CNN
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+F 3 "" H 9200 4350 50  0001 C CNN
+	1    9200 4350
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+NoConn ~ 7800 4650
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+Text GLabel 5750 4150 0    50   Input ~ 0
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+Text GLabel 5750 3950 0    50   Input ~ 0
+TOOL0_TX
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+Wire Wire Line
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+nRESET_OUT
+Wire Wire Line
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+Wire Wire Line
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+TOOL0
+Wire Wire Line
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+F 2 "Package_DIP:DIP-16_W7.62mm" H 3850 4850 50  0001 C CNN
+F 3 "http://www.intersil.com/content/dam/Intersil/documents/cd40/cd4051bms-52bms-53bms.pdf" H 3850 4850 50  0001 C CNN
+	1    3850 4850
+	1    0    0    -1  
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+F 0 "#PWR?" H 9200 5400 50  0001 C CNN
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+F 2 "" H 9200 5650 50  0001 C CNN
+F 3 "" H 9200 5650 50  0001 C CNN
+	1    9200 5650
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+$EndComp
+Wire Wire Line
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+F 2 "" H 10600 4350 50  0001 C CNN
+F 3 "" H 10600 4350 50  0001 C CNN
+	1    10600 4350
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+$EndComp
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+F 3 "" H 10050 3800 50  0001 C CNN
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+Wire Wire Line
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+PICO_STDIO_UART_TX
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+PICO_STDIO_UART_RX
+$Comp
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+F 2 "" H 5950 4600 50  0001 C CNN
+F 3 "" H 5950 4600 50  0001 C CNN
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+F 0 "#PWR?" H 3900 5600 50  0001 C CNN
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+F 2 "" H 3900 5850 50  0001 C CNN
+F 3 "" H 3900 5850 50  0001 C CNN
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+F 2 "" H 3200 5150 50  0001 C CNN
+F 3 "" H 3200 5150 50  0001 C CNN
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+U 1 1 61AE8DAA
+P 2200 4950
+F 0 "U4" H 2200 5317 50  0000 C CNN
+F 1 "AS358P-E1" H 2200 5226 50  0000 C CNN
+F 2 "Package_DIP:DIP-8_W7.62mm" H 2200 4950 50  0001 C CNN
+F 3 "http://www.ti.com/lit/ds/symlink/lm2904-n.pdf" H 2200 4950 50  0001 C CNN
+	1    2200 4950
+	1    0    0    -1  
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+Wire Wire Line
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+U 1 1 61CF17E5
+P 6250 3500
+F 0 "#PWR?" H 6250 3350 50  0001 C CNN
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+F 2 "" H 6250 3500 50  0001 C CNN
+F 3 "" H 6250 3500 50  0001 C CNN
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+	1    0    0    -1  
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+Wire Wire Line
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+$Comp
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+U 1 1 61AEFF98
+P 6250 3750
+F 0 "R1" H 6320 3796 50  0000 L CNN
+F 1 "47k" H 6320 3705 50  0000 L CNN
+F 2 "" V 6180 3750 50  0001 C CNN
+F 3 "~" H 6250 3750 50  0001 C CNN
+	1    6250 3750
+	1    0    0    -1  
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+Text Label 6300 4150 0    50   ~ 0
+TOOL0
+Text Notes 6350 3600 0    50   ~ 0
+TOOL0 needs a pullup, it\ngoes low when glitching
+Text Notes 7550 3300 0    50   ~ 0
+UART stdio for debug
+Text Notes 8050 3000 0    50   ~ 0
+use a Pico to control the glitching process: monitor TRIG_IN for\nwhen glitching should happen, use GLITCH_OUT to do a glitch,\nand use TOOL0 and ~RESET~ to control the MCU
+Text Notes 10550 3900 0    50   ~ 0
+Pico is also the\npower source\nfor everything
+Wire Notes Line
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+Wire Notes Line
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+Wire Notes Line
+	5450 4250 5150 4250
+Wire Notes Line
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+Wire Notes Line
+	6000 3550 5600 3550
+Text Notes 4900 3850 0    50   ~ 0
+protection diodes to\navoid short-circuits.\nuse TOOL_TX/RX if\nyou use a normal\nUART, or use TOOL0\ndirectly when you\nhave a specific impl
+Text Notes 5800 5800 0    50   ~ 0
+this is the REGC cap,\nRL78 needs it to work
+Text Notes 4200 5350 0    50   ~ 0
+use MAX4619CPE to select between\nnormal & low/glitch voltage. use 3\ncircuits at once to minimize the\nparasitic resistance (I don't have\nenough wires for that so I didn't)
+Text Notes 6850 5750 0    50   ~ 0
+bypass/decoupling\ncap for testing how\ngood the glitching\nis. tweak value, but\nDO NOT PLACE\nwhen beginning
+$Comp
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+P 6700 5350
+F 0 "#PWR?" H 6700 5100 50  0001 C CNN
+F 1 "GND" H 6705 5177 50  0000 C CNN
+F 2 "" H 6700 5350 50  0001 C CNN
+F 3 "" H 6700 5350 50  0001 C CNN
+	1    6700 5350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6700 5250 6700 5350
+$Comp
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+P 6700 5100
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+F 1 "Ctest, DNP" H 6815 5055 50  0000 L CNN
+F 2 "" H 6738 4950 50  0001 C CNN
+F 3 "~" H 6700 5100 50  0001 C CNN
+	1    6700 5100
+	1    0    0    -1  
+$EndComp
+Text Label 4550 4850 0    50   ~ 0
+Vdd_TO_RL78
+Text Notes 1550 5950 0    50   ~ 0
+opamp needed: my trimpot is 10k,\n3.3V/10k = 0.3mA to MCU...\nopamp in buffer mode fixes this\n& gives MCU all current it wants
+Wire Wire Line
+	1800 5600 1800 5050
+Wire Wire Line
+	2600 4950 2600 5600
+Wire Wire Line
+	2600 5600 1800 5600
+Wire Wire Line
+	2100 5350 2100 5250
+$Comp
+L power:GND #PWR?
+U 1 1 61D135B5
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+F 0 "#PWR?" H 2100 5100 50  0001 C CNN
+F 1 "GND" H 2105 5177 50  0000 C CNN
+F 2 "" H 2100 5350 50  0001 C CNN
+F 3 "" H 2100 5350 50  0001 C CNN
+	1    2100 5350
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 3 1 61AEA01B
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+F 0 "U4" H 2158 4950 50  0001 L CNN
+F 1 "AS358P-E1" H 2158 4905 50  0001 L CNN
+F 2 "Package_DIP:DIP-8_W7.62mm" H 2200 4950 50  0001 C CNN
+F 3 "http://www.ti.com/lit/ds/symlink/lm2904-n.pdf" H 2200 4950 50  0001 C CNN
+	3    2200 4950
+	1    0    0    -1  
+$EndComp
+Connection ~ 2100 5250
+Connection ~ 2100 4550
+Wire Wire Line
+	2100 4550 2100 4450
+Wire Wire Line
+	2100 4650 2100 4550
+Text Notes 600  5200 0    50   ~ 0
+trimpot to select\n"low"/glitch voltage\n(regular voltage is 3.3V)
+Wire Wire Line
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+Wire Wire Line
+	1600 5000 1600 5250
+Wire Wire Line
+	1600 4550 1600 4700
+Wire Wire Line
+	2100 4550 1600 4550
+$Comp
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+F 0 "RV1" H 1530 4896 50  0000 R CNN
+F 1 "R_POT_TRIM" H 1530 4805 50  0000 R CNN
+F 2 "" H 1600 4850 50  0001 C CNN
+F 3 "~" H 1600 4850 50  0001 C CNN
+	1    1600 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:+3.3V #PWR?
+U 1 1 61D0B772
+P 2100 4450
+F 0 "#PWR?" H 2100 4300 50  0001 C CNN
+F 1 "+3.3V" H 2115 4623 50  0000 C CNN
+F 2 "" H 2100 4450 50  0001 C CNN
+F 3 "" H 2100 4450 50  0001 C CNN
+	1    2100 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:+3.3V #PWR?
+U 1 1 61CFB76A
+P 3300 3700
+F 0 "#PWR?" H 3300 3550 50  0001 C CNN
+F 1 "+3.3V" H 3315 3873 50  0000 C CNN
+F 2 "" H 3300 3700 50  0001 C CNN
+F 3 "" H 3300 3700 50  0001 C CNN
+	1    3300 3700
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
				`@ -0,0 +1 @@`
				`(kicad_pcb (version 4) (host kicad "dummy file") )`