98 lines
2.0 KiB
Plaintext
98 lines
2.0 KiB
Plaintext
digraph {
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"4004" -> {TMS1000 "8008"}
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TMS1000 -> {"17K" MSP430}
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"8008" -> {"8080" "8048"}
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"8080" -> {"8088" "8086" Z80 "87AD" LR35902 ST6}
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"8086" -> {V60 x86}
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Z80 -> {Z8 Z180 Z800 Z8000 LR35902 "TLCS-90" "87AD" eZ80}
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"87AD" -> "78K0"
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"17K" -> "78K0"
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"78K0" -> "78K0S"
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"78K0" -> "78K0R"
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"78K0R" -> RL78
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"TLCS-90" -> {"TLCS-870" "TLCS-900"}
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Z8000 -> Z80000
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Z180 -> Z280
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Z800 -> Z280
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Z280 -> Z380
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Z8 -> eZ8
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//eZ80 -> eZ8
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"8048" -> "8051"
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ST6 -> ST7
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ST7 -> STM8
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"6800" -> {"6801" "6809" "6502" "68000"}
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"6801" -> {"68HC05" "68HC08" "68HC11"}
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"68HC11" -> {"68HC12" "68HC16"}
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"6502" -> "65816"
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"68HC12" -> S12
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S12 -> MagniV
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PDP11 -> VAX
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PDP11 -> MSP430
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VAX -> {"68000" "V60, V70, V80" "H8/300" "DEC Alpha"}
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"V60, V70, V80" -> "V810, V830"
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"V810, V830" -> V850
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V850 -> RH850
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"68000" -> {"680x0" ColdFire "H8/300" /*"88000"*/}
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"680x0" -> "Apollo 68080"
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"H8/300" -> {"H8/300H" "H8/300L"}
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"H8/300H" -> H8S
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H8S -> H8SX
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H8SX -> RX
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V850 -> RX
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RL78 -> RX
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SuperH -> RX, ARMv4, ARCompact, "RISC-V"
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"Super FX" -> ARC
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ARC -> ARCompact
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RISC -> {i960 Am29000 ARMv2 SuperH "PA-RISC" "801" ROMP SPARC DLX OpenRISC1000 AVR ARC "88000" "RISC-V"}
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MIPS -> {PRISM OpenRISC1000 Xtensa LoongArch "RISC-V" "C-SKY"}
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"801" -> PowerPC
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ROMP -> PowerPC
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"88000" -> PowerPC
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DLX -> MicroBlaze
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OpenRISC1000 -> LM32, "RISC-V"
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SPARC -> {UltraSPARC SPARCLite}
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SuperH -> {CR16 Xtensa}
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PRISM -> "DEC Alpha"
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ARMv2 -> ARMv4
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ARMv4 -> ARMv5
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ARMv5 -> ARMv6
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ARMv6 -> {"Cortex-A" "Cortex-R" "Cortex-M"}
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ARMv4 -> "Cortex-M"
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"DEC Alpha" -> {StrongARM "Cortex-A"}
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"Cortex-A" -> {"Cortex-X" Neoverse}
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"PA-RISC" -> Itanium
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x86 -> Itanium
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PowerPC -> {Itanium "C-SKY"}
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i960 -> Itanium
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x86 -> AMD64
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//"8051" -> AVR
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AVR -> AVR32
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ARMv4 -> AVR32
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ARMv4 -> StrongARM
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StrongARM -> XScale
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SPARCLite -> FR
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FR -> "FR-V"
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"56000" -> {Teak Oak}
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Oak -> Teak
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Teak -> "CEVA-X"
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TMS320 -> {"FR-V" "CEVA-X" SHARC Hexagon Xtensa}
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SHARC -> {Blackfin TigerSHARC}
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XScale -> Blackfin
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}
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