2012-12-29 21:22:10 +00:00
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/*
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* This file is part of the libsigrok project.
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*
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* Copyright (C) 2012 Martin Ling <martin-git@earth.li>
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2013-04-08 10:01:00 +00:00
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* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
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2013-11-01 11:05:49 +00:00
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* Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
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2012-12-29 21:22:10 +00:00
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdlib.h>
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2012-12-30 03:17:56 +00:00
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#include <stdarg.h>
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#include <unistd.h>
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#include <errno.h>
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2013-04-07 23:12:42 +00:00
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#include <string.h>
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2013-04-11 14:06:55 +00:00
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#include <math.h>
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2013-11-01 11:05:49 +00:00
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#include <ctype.h>
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#include <time.h>
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2012-12-29 21:22:10 +00:00
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#include <glib.h>
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#include "libsigrok.h"
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#include "libsigrok-internal.h"
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#include "protocol.h"
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2013-11-01 11:05:49 +00:00
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/*
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* This is a unified protocol driver for the DS1000 and DS2000 series.
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*
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* DS1000 support tested with a Rigol DS1102D.
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*
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* DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02.
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*
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* The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think)
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* standard. If you want to read it - it costs real money...
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*
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* Every response from the scope has a linefeed appended because the
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* standard says so. In principle this could be ignored because sending the
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* next command clears the output queue of the scope. This driver tries to
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* avoid doing that because it may cause an error being generated inside the
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* scope and who knows what bugs the firmware has WRT this.
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*
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* Waveform data is transferred in a format called "arbitrary block program
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* data" specified in IEEE 488.2. See Agilents programming manuals for their
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* 2000/3000 series scopes for a nice description.
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*
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* Each data block from the scope has a header, e.g. "#900000001400".
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* The '#' marks the start of a block.
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* Next is one ASCII decimal digit between 1 and 9, this gives the number of
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* ASCII decimal digits following.
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* Last are the ASCII decimal digits giving the number of bytes (not
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* samples!) in the block.
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*
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* After this header as many data bytes as indicated follow.
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*
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* Each data block has a trailing linefeed too.
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*/
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static int get_cfg(const struct sr_dev_inst *sdi, char *cmd, char *reply, size_t maxlen);
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static int get_cfg_int(const struct sr_dev_inst *sdi, char *cmd, int *i);
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static int parse_int(const char *str, int *ret)
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{
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char *e;
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long tmp;
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errno = 0;
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tmp = strtol(str, &e, 10);
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if (e == str || *e != '\0') {
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sr_dbg("Failed to parse integer: '%s'", str);
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return SR_ERR;
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}
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if (errno) {
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sr_dbg("Failed to parse integer: '%s', numerical overflow", str);
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return SR_ERR;
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}
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if (tmp > INT_MAX || tmp < INT_MIN) {
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sr_dbg("Failed to parse integer: '%s', value to large/small", str);
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return SR_ERR;
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}
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*ret = (int)tmp;
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return SR_OK;
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}
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/*
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* Waiting for a trigger event will return a timeout after 2, 3 seconds in
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* order to not block the application.
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*/
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static int rigol_ds2xx2_trigger_wait(const struct sr_dev_inst *sdi)
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{
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char buf[20];
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struct dev_context *devc;
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time_t start;
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if (!(devc = sdi->priv))
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return SR_ERR;
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start = time(NULL);
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/*
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* Trigger status may return:
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* "TD" - triggered
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* "AUTO" - autotriggered
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* "RUN" - running
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* "WAIT" - waiting for trigger
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* "STOP" - stopped
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*/
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if (devc->trigger_wait_status == 1) {
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do {
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if (time(NULL) - start >= 3) {
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sr_dbg("Timeout waiting for trigger");
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return SR_ERR_TIMEOUT;
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}
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if (get_cfg(sdi, ":TRIG:STAT?", buf, sizeof(buf)) != SR_OK)
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return SR_ERR;
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} while (buf[0] == 'T' || buf[0] == 'A');
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devc->trigger_wait_status = 2;
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}
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if (devc->trigger_wait_status == 2) {
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do {
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if (time(NULL) - start >= 3) {
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sr_dbg("Timeout waiting for trigger");
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return SR_ERR_TIMEOUT;
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}
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if (get_cfg(sdi, ":TRIG:STAT?", buf, sizeof(buf)) != SR_OK)
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return SR_ERR;
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} while (buf[0] != 'T' && buf[0] != 'A');
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devc->trigger_wait_status = 0;
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}
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return SR_OK;
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}
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/*
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* This needs to wait for a new trigger event to ensure that sample data is
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* not returned twice.
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*
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* Unfortunately this will never really work because for sufficiently fast
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* timebases it just can't catch the status changes.
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*
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* What would be needed is a trigger event register with autoreset like the
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* Agilents have. The Rigols don't seem to have anything like this.
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*
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* The workaround is to only wait for the trigger when the timebase is slow
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* enough. Of course this means that for faster timebases sample data can be
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* returned multiple times.
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*/
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SR_PRIV int rigol_ds2xx2_acquisition_start(const struct sr_dev_inst *sdi,
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gboolean wait_for_trigger)
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{
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struct dev_context *devc;
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if (!(devc = sdi->priv))
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return SR_ERR;
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sr_dbg("Starting acquisition on channel %d",
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devc->channel_frame->index + 1);
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if (rigol_ds_send(sdi, ":WAV:FORM BYTE") != SR_OK)
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return SR_ERR;
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if (rigol_ds_send(sdi, ":WAV:SOUR CHAN%d",
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devc->channel_frame->index + 1) != SR_OK)
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return SR_ERR;
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if (rigol_ds_send(sdi, ":WAV:MODE NORM") != SR_OK)
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return SR_ERR;
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devc->num_frame_bytes = 0;
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devc->num_block_bytes = 0;
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/* only wait for trigger if timbase 50 msecs/DIV or slower */
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if (wait_for_trigger && devc->timebase > 0.0499)
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{
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devc->trigger_wait_status = 1;
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} else {
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devc->trigger_wait_status = 0;
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}
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return SR_OK;
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}
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static int rigol_ds2xx2_read_header(struct sr_serial_dev_inst *serial)
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{
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char start[3], length[10];
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int len, tmp;
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/* Read the hashsign and length digit. */
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tmp = serial_read(serial, start, 2);
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start[2] = '\0';
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if (tmp != 2)
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{
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sr_err("Failed to read first two bytes of data block header.");
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return -1;
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}
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if (start[0] != '#' || !isdigit(start[1]) || start[1] == '0')
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{
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sr_err("Received invalid data block header start '%s'.", start);
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return -1;
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}
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len = atoi(start + 1);
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/* Read the data length. */
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tmp = serial_read(serial, length, len);
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length[len] = '\0';
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if (tmp != len)
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{
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sr_err("Failed to read %d bytes of data block length.", len);
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return -1;
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}
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if (parse_int(length, &len) != SR_OK)
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{
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sr_err("Received invalid data block length '%s'.", length);
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return -1;
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}
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sr_dbg("Received data block header: %s%s -> block length %d", start, length, len);
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return len;
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}
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2013-10-31 17:31:39 +00:00
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SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data)
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2012-12-29 21:22:10 +00:00
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{
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2012-12-30 03:17:56 +00:00
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struct sr_dev_inst *sdi;
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2013-04-22 15:12:06 +00:00
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struct sr_serial_dev_inst *serial;
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2012-12-29 21:22:10 +00:00
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struct dev_context *devc;
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2012-12-30 03:17:56 +00:00
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struct sr_datafeed_packet packet;
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struct sr_datafeed_analog analog;
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2013-04-14 01:21:55 +00:00
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struct sr_datafeed_logic logic;
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2013-11-01 11:05:49 +00:00
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unsigned char buf[DS2000_ANALOG_WAVEFORM_SIZE];
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2013-04-11 14:06:55 +00:00
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double vdiv, offset;
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2013-11-01 11:05:49 +00:00
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float data[DS2000_ANALOG_WAVEFORM_SIZE];
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int len, i, waveform_size, vref;
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2013-04-14 01:21:55 +00:00
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struct sr_probe *probe;
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2012-12-29 21:22:10 +00:00
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2013-05-10 16:30:32 +00:00
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(void)fd;
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2013-04-22 15:12:06 +00:00
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2012-12-29 21:22:10 +00:00
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if (!(sdi = cb_data))
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return TRUE;
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if (!(devc = sdi->priv))
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return TRUE;
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2013-04-22 15:12:06 +00:00
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serial = sdi->conn;
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2012-12-29 21:22:10 +00:00
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if (revents == G_IO_IN) {
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2013-11-01 11:05:49 +00:00
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if (devc->trigger_wait_status > 0) {
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if (rigol_ds2xx2_trigger_wait(sdi) != SR_OK)
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return TRUE;
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}
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if (devc->model->series == 2 && devc->num_block_bytes == 0) {
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sr_dbg("New block header expected");
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if (rigol_ds_send(sdi, ":WAV:DATA?") != SR_OK)
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return TRUE;
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len = rigol_ds2xx2_read_header(serial);
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if (len == -1)
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return TRUE;
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/* At slow timebases the scope sometimes returns
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* "short" data blocks, with apparently no way to
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* get the rest of the data. Discard these, the
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* complete data block will appear eventually.
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*/
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if (len < DS2000_ANALOG_WAVEFORM_SIZE) {
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sr_dbg("Discarding short data block");
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serial_read(serial, buf, len + 1);
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return TRUE;
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}
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devc->num_block_bytes = len;
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devc->num_block_read = 0;
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}
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2013-04-14 01:21:55 +00:00
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probe = devc->channel_frame;
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2013-11-01 11:05:49 +00:00
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if (devc->model->series == 2) {
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len = devc->num_block_bytes - devc->num_block_read;
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len = serial_read(serial, buf,
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len < DS2000_ANALOG_WAVEFORM_SIZE ? len : DS2000_ANALOG_WAVEFORM_SIZE);
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} else {
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waveform_size = probe->type == SR_PROBE_ANALOG ?
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DS1000_ANALOG_WAVEFORM_SIZE : DIGITAL_WAVEFORM_SIZE;
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len = serial_read(serial, buf, waveform_size - devc->num_frame_bytes);
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}
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2013-01-03 18:04:11 +00:00
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sr_dbg("Received %d bytes.", len);
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2012-12-30 03:17:56 +00:00
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if (len == -1)
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return TRUE;
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2013-04-07 22:38:58 +00:00
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2013-04-14 00:58:35 +00:00
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if (devc->num_frame_bytes == 0) {
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2013-04-07 22:38:58 +00:00
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/* Start of a new frame. */
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packet.type = SR_DF_FRAME_BEGIN;
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sr_session_send(sdi, &packet);
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}
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2013-04-14 01:21:55 +00:00
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if (probe->type == SR_PROBE_ANALOG) {
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2013-11-01 11:05:49 +00:00
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if (devc->model->series == 2)
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devc->num_block_read += len;
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vref = devc->vert_reference[probe->index];
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vdiv = devc->vdiv[probe->index] / 25.6;
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offset = devc->vert_offset[probe->index];
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if (devc->model->series == 2)
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for (i = 0; i < len; i++)
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data[i] = ((int)buf[i] - vref) * vdiv - offset;
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else
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for (i = 0; i < len; i++)
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data[i] = (128 - buf[i]) * vdiv - offset;
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2013-04-14 01:21:55 +00:00
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analog.probes = g_slist_append(NULL, probe);
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analog.num_samples = len;
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analog.data = data;
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analog.mq = SR_MQ_VOLTAGE;
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analog.unit = SR_UNIT_VOLT;
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analog.mqflags = 0;
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packet.type = SR_DF_ANALOG;
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packet.payload = &analog;
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sr_session_send(cb_data, &packet);
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g_slist_free(analog.probes);
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2013-11-01 11:05:49 +00:00
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if (devc->model->series == 2) {
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devc->num_frame_bytes += len;
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if (devc->num_frame_bytes < DS2000_ANALOG_WAVEFORM_SIZE)
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/* Don't have the whole frame yet. */
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return TRUE;
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sr_dbg("Frame completed, %d samples", devc->num_frame_bytes);
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} else {
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if (len != DS1000_ANALOG_WAVEFORM_SIZE)
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/* Don't have the whole frame yet. */
|
|
|
|
return TRUE;
|
|
|
|
}
|
2013-04-14 01:21:55 +00:00
|
|
|
} else {
|
|
|
|
logic.length = len - 10;
|
|
|
|
logic.unitsize = 2;
|
|
|
|
logic.data = buf + 10;
|
|
|
|
packet.type = SR_DF_LOGIC;
|
|
|
|
packet.payload = &logic;
|
|
|
|
sr_session_send(cb_data, &packet);
|
|
|
|
|
|
|
|
if (len != DIGITAL_WAVEFORM_SIZE)
|
|
|
|
/* Don't have the whole frame yet. */
|
|
|
|
return TRUE;
|
2013-04-14 00:58:35 +00:00
|
|
|
}
|
2013-04-07 22:38:58 +00:00
|
|
|
|
2013-04-11 14:06:55 +00:00
|
|
|
/* End of the frame. */
|
|
|
|
packet.type = SR_DF_FRAME_END;
|
|
|
|
sr_session_send(sdi, &packet);
|
2013-11-01 11:05:49 +00:00
|
|
|
if (devc->model->series == 1)
|
|
|
|
devc->num_frame_bytes = 0;
|
2013-04-11 14:06:55 +00:00
|
|
|
|
2013-04-14 01:21:55 +00:00
|
|
|
if (devc->enabled_analog_probes
|
|
|
|
&& devc->channel_frame == devc->enabled_analog_probes->data
|
|
|
|
&& devc->enabled_analog_probes->next != NULL) {
|
|
|
|
/* We got the frame for the first analog channel, but
|
|
|
|
* there's a second analog channel. */
|
2013-11-07 23:13:30 +00:00
|
|
|
devc->channel_frame = devc->enabled_analog_probes->next->data;
|
2013-11-01 11:05:49 +00:00
|
|
|
if (devc->model->series == 2) {
|
|
|
|
/* Do not wait for trigger to try and keep channel data related. */
|
|
|
|
rigol_ds2xx2_acquisition_start(sdi, FALSE);
|
|
|
|
} else {
|
|
|
|
rigol_ds_send(sdi, ":WAV:DATA? CHAN%c",
|
|
|
|
devc->channel_frame->name[2]);
|
|
|
|
}
|
2013-04-11 14:06:55 +00:00
|
|
|
} else {
|
2013-04-14 01:21:55 +00:00
|
|
|
/* Done with both analog channels in this frame. */
|
|
|
|
if (devc->enabled_digital_probes
|
|
|
|
&& devc->channel_frame != devc->enabled_digital_probes->data) {
|
|
|
|
/* Now we need to get the digital data. */
|
|
|
|
devc->channel_frame = devc->enabled_digital_probes->data;
|
2013-10-31 17:31:39 +00:00
|
|
|
rigol_ds_send(sdi, ":WAV:DATA? DIG");
|
2013-04-14 01:21:55 +00:00
|
|
|
} else if (++devc->num_frames == devc->limit_frames) {
|
|
|
|
/* End of last frame. */
|
2013-11-15 15:54:55 +00:00
|
|
|
packet.type = SR_DF_END;
|
|
|
|
sr_session_send(sdi, &packet);
|
2013-04-07 22:38:58 +00:00
|
|
|
sdi->driver->dev_acquisition_stop(sdi, cb_data);
|
2013-04-11 14:06:55 +00:00
|
|
|
} else {
|
2013-04-14 01:21:55 +00:00
|
|
|
/* Get the next frame, starting with the first analog channel. */
|
2013-11-01 11:05:49 +00:00
|
|
|
if (devc->model->series == 2) {
|
|
|
|
if (devc->enabled_analog_probes) {
|
2013-11-07 23:13:30 +00:00
|
|
|
devc->channel_frame = devc->enabled_analog_probes->data;
|
2013-11-01 11:05:49 +00:00
|
|
|
/* Must wait for trigger because at
|
|
|
|
* slow timebases the scope will
|
|
|
|
* return old data otherwise. */
|
|
|
|
rigol_ds2xx2_acquisition_start(sdi, TRUE);
|
|
|
|
}
|
2013-04-14 01:21:55 +00:00
|
|
|
} else {
|
2013-11-01 11:05:49 +00:00
|
|
|
if (devc->enabled_analog_probes) {
|
|
|
|
devc->channel_frame = devc->enabled_analog_probes->data;
|
|
|
|
rigol_ds_send(sdi, ":WAV:DATA? CHAN%c",
|
|
|
|
devc->channel_frame->name[2]);
|
|
|
|
} else {
|
|
|
|
devc->channel_frame = devc->enabled_digital_probes->data;
|
|
|
|
rigol_ds_send(sdi, ":WAV:DATA? DIG");
|
|
|
|
}
|
2013-04-14 01:21:55 +00:00
|
|
|
}
|
2013-04-11 14:06:55 +00:00
|
|
|
}
|
2013-04-07 22:38:58 +00:00
|
|
|
}
|
2012-12-29 21:22:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return TRUE;
|
|
|
|
}
|
2012-12-30 03:17:56 +00:00
|
|
|
|
2013-10-31 17:31:39 +00:00
|
|
|
SR_PRIV int rigol_ds_send(const struct sr_dev_inst *sdi, const char *format, ...)
|
2012-12-30 03:17:56 +00:00
|
|
|
{
|
|
|
|
va_list args;
|
|
|
|
char buf[256];
|
2013-04-07 23:12:42 +00:00
|
|
|
int len, out, ret;
|
2013-01-03 18:04:11 +00:00
|
|
|
|
2012-12-30 03:17:56 +00:00
|
|
|
va_start(args, format);
|
2013-04-11 14:06:55 +00:00
|
|
|
len = vsnprintf(buf, 255, format, args);
|
2012-12-30 03:17:56 +00:00
|
|
|
va_end(args);
|
2013-04-07 23:12:42 +00:00
|
|
|
strcat(buf, "\n");
|
|
|
|
len++;
|
2013-04-22 15:12:06 +00:00
|
|
|
out = serial_write(sdi->conn, buf, len);
|
2013-04-07 23:12:42 +00:00
|
|
|
buf[len - 1] = '\0';
|
|
|
|
if (out != len) {
|
|
|
|
sr_dbg("Only sent %d/%d bytes of '%s'.", out, len, buf);
|
|
|
|
ret = SR_ERR;
|
|
|
|
} else {
|
2013-04-11 14:06:55 +00:00
|
|
|
sr_spew("Sent '%s'.", buf);
|
2013-04-07 23:12:42 +00:00
|
|
|
ret = SR_OK;
|
|
|
|
}
|
2013-01-03 18:04:11 +00:00
|
|
|
|
2013-04-07 23:12:42 +00:00
|
|
|
return ret;
|
2012-12-30 03:17:56 +00:00
|
|
|
}
|
2013-04-11 14:06:55 +00:00
|
|
|
|
2013-11-01 11:05:49 +00:00
|
|
|
static int get_cfg(const struct sr_dev_inst *sdi, char *cmd, char *reply, size_t maxlen)
|
2013-04-11 14:06:55 +00:00
|
|
|
{
|
|
|
|
int len;
|
2013-11-01 11:05:49 +00:00
|
|
|
struct dev_context *devc = sdi->priv;
|
2013-04-11 14:06:55 +00:00
|
|
|
|
2013-10-31 17:31:39 +00:00
|
|
|
if (rigol_ds_send(sdi, cmd) != SR_OK)
|
2013-04-11 14:06:55 +00:00
|
|
|
return SR_ERR;
|
|
|
|
|
2013-11-01 11:05:49 +00:00
|
|
|
if ((len = serial_read(sdi->conn, reply, maxlen - 1)) < 0)
|
2013-04-11 14:06:55 +00:00
|
|
|
return SR_ERR;
|
|
|
|
reply[len] = '\0';
|
2013-11-01 11:05:49 +00:00
|
|
|
|
|
|
|
if (devc->model->series == 2) {
|
|
|
|
/* get rid of trailing linefeed */
|
|
|
|
if (len >= 1 && reply[len-1] == '\n')
|
|
|
|
reply[len-1] = '\0';
|
|
|
|
}
|
|
|
|
|
2013-04-11 14:06:55 +00:00
|
|
|
sr_spew("Received '%s'.", reply);
|
|
|
|
|
|
|
|
return SR_OK;
|
|
|
|
}
|
|
|
|
|
2013-11-01 11:05:49 +00:00
|
|
|
static int get_cfg_int(const struct sr_dev_inst *sdi, char *cmd, int *i)
|
|
|
|
{
|
|
|
|
char buf[32];
|
|
|
|
|
|
|
|
if (get_cfg(sdi, cmd, buf, sizeof(buf)) != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
|
|
|
|
if (parse_int(buf, i) != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
|
|
|
|
return SR_OK;
|
|
|
|
}
|
|
|
|
|
2013-04-11 14:06:55 +00:00
|
|
|
static int get_cfg_float(const struct sr_dev_inst *sdi, char *cmd, float *f)
|
|
|
|
{
|
2013-11-01 11:05:49 +00:00
|
|
|
char buf[32], *e;
|
2013-04-11 14:06:55 +00:00
|
|
|
|
2013-11-01 11:05:49 +00:00
|
|
|
if (get_cfg(sdi, cmd, buf, sizeof(buf)) != SR_OK)
|
2013-04-11 14:06:55 +00:00
|
|
|
return SR_ERR;
|
|
|
|
*f = strtof(buf, &e);
|
2013-04-12 16:44:28 +00:00
|
|
|
if (e == buf || (fpclassify(*f) & (FP_ZERO | FP_NORMAL)) == 0) {
|
2013-04-11 14:06:55 +00:00
|
|
|
sr_dbg("failed to parse response to '%s': '%s'", cmd, buf);
|
|
|
|
return SR_ERR;
|
|
|
|
}
|
|
|
|
|
|
|
|
return SR_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int get_cfg_string(const struct sr_dev_inst *sdi, char *cmd, char **buf)
|
|
|
|
{
|
|
|
|
if (!(*buf = g_try_malloc0(256)))
|
2013-04-12 16:44:28 +00:00
|
|
|
return SR_ERR_MALLOC;
|
2013-04-11 14:06:55 +00:00
|
|
|
|
2013-11-01 11:05:49 +00:00
|
|
|
if (get_cfg(sdi, cmd, *buf, 256) != SR_OK)
|
2013-04-11 14:06:55 +00:00
|
|
|
return SR_ERR;
|
|
|
|
|
|
|
|
return SR_OK;
|
|
|
|
}
|
|
|
|
|
2013-10-31 17:31:39 +00:00
|
|
|
SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi)
|
2013-04-11 14:06:55 +00:00
|
|
|
{
|
|
|
|
struct dev_context *devc;
|
2013-04-14 01:21:55 +00:00
|
|
|
char *t_s, *cmd;
|
|
|
|
int i, res;
|
2013-04-11 14:06:55 +00:00
|
|
|
|
|
|
|
devc = sdi->priv;
|
|
|
|
|
2013-04-14 01:21:55 +00:00
|
|
|
/* Analog channel state. */
|
2013-04-11 14:06:55 +00:00
|
|
|
if (get_cfg_string(sdi, ":CHAN1:DISP?", &t_s) != SR_OK)
|
|
|
|
return SR_ERR;
|
2013-11-01 11:05:49 +00:00
|
|
|
devc->analog_channels[0] = !strcmp(t_s, "ON") || !strcmp(t_s, "1");
|
2013-04-11 14:06:55 +00:00
|
|
|
g_free(t_s);
|
|
|
|
if (get_cfg_string(sdi, ":CHAN2:DISP?", &t_s) != SR_OK)
|
|
|
|
return SR_ERR;
|
2013-11-01 11:05:49 +00:00
|
|
|
devc->analog_channels[1] = !strcmp(t_s, "ON") || !strcmp(t_s, "1");
|
2013-04-11 14:06:55 +00:00
|
|
|
g_free(t_s);
|
2013-04-14 01:21:55 +00:00
|
|
|
sr_dbg("Current analog channel state CH1 %s CH2 %s",
|
|
|
|
devc->analog_channels[0] ? "on" : "off",
|
|
|
|
devc->analog_channels[1] ? "on" : "off");
|
|
|
|
|
|
|
|
/* Digital channel state. */
|
2013-11-01 11:05:49 +00:00
|
|
|
if (devc->model->has_digital) {
|
2013-04-14 01:21:55 +00:00
|
|
|
sr_dbg("Current digital channel state:");
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
|
|
cmd = g_strdup_printf(":DIG%d:TURN?", i);
|
|
|
|
res = get_cfg_string(sdi, cmd, &t_s);
|
|
|
|
g_free(cmd);
|
|
|
|
if (res != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
devc->digital_channels[i] = !strcmp(t_s, "ON") ? TRUE : FALSE;
|
|
|
|
g_free(t_s);
|
|
|
|
sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off");
|
|
|
|
}
|
|
|
|
}
|
2013-04-11 14:06:55 +00:00
|
|
|
|
|
|
|
/* Timebase. */
|
|
|
|
if (get_cfg_float(sdi, ":TIM:SCAL?", &devc->timebase) != SR_OK)
|
|
|
|
return SR_ERR;
|
2013-11-01 11:05:49 +00:00
|
|
|
sr_dbg("Current timebase %g", devc->timebase);
|
2013-04-11 14:06:55 +00:00
|
|
|
|
|
|
|
/* Vertical gain. */
|
|
|
|
if (get_cfg_float(sdi, ":CHAN1:SCAL?", &devc->vdiv[0]) != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
if (get_cfg_float(sdi, ":CHAN2:SCAL?", &devc->vdiv[1]) != SR_OK)
|
|
|
|
return SR_ERR;
|
2013-11-01 11:05:49 +00:00
|
|
|
sr_dbg("Current vertical gain CH1 %g CH2 %g", devc->vdiv[0], devc->vdiv[1]);
|
|
|
|
|
|
|
|
if (devc->model->series == 2) {
|
|
|
|
/* Vertical reference - not certain if this is the place to read it. */
|
|
|
|
if (rigol_ds_send(sdi, ":WAV:SOUR CHAN1") != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
if (get_cfg_int(sdi, ":WAV:YREF?", &devc->vert_reference[0]) != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
if (rigol_ds_send(sdi, ":WAV:SOUR CHAN2") != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
if (get_cfg_int(sdi, ":WAV:YREF?", &devc->vert_reference[1]) != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
sr_dbg("Current vertical reference CH1 %d CH2 %d",
|
|
|
|
devc->vert_reference[0], devc->vert_reference[1]);
|
|
|
|
}
|
2013-04-11 14:06:55 +00:00
|
|
|
|
|
|
|
/* Vertical offset. */
|
|
|
|
if (get_cfg_float(sdi, ":CHAN1:OFFS?", &devc->vert_offset[0]) != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
if (get_cfg_float(sdi, ":CHAN2:OFFS?", &devc->vert_offset[1]) != SR_OK)
|
|
|
|
return SR_ERR;
|
2013-11-01 11:05:49 +00:00
|
|
|
sr_dbg("Current vertical offset CH1 %g CH2 %g", devc->vert_offset[0],
|
2013-04-11 14:06:55 +00:00
|
|
|
devc->vert_offset[1]);
|
|
|
|
|
|
|
|
/* Coupling. */
|
|
|
|
if (get_cfg_string(sdi, ":CHAN1:COUP?", &devc->coupling[0]) != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
if (get_cfg_string(sdi, ":CHAN2:COUP?", &devc->coupling[1]) != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
sr_dbg("Current coupling CH1 %s CH2 %s", devc->coupling[0],
|
|
|
|
devc->coupling[1]);
|
|
|
|
|
|
|
|
/* Trigger source. */
|
|
|
|
if (get_cfg_string(sdi, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
sr_dbg("Current trigger source %s", devc->trigger_source);
|
|
|
|
|
|
|
|
/* Horizontal trigger position. */
|
|
|
|
if (get_cfg_float(sdi, ":TIM:OFFS?", &devc->horiz_triggerpos) != SR_OK)
|
|
|
|
return SR_ERR;
|
2013-11-01 11:05:49 +00:00
|
|
|
sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos);
|
2013-04-11 14:06:55 +00:00
|
|
|
|
|
|
|
/* Trigger slope. */
|
|
|
|
if (get_cfg_string(sdi, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK)
|
|
|
|
return SR_ERR;
|
|
|
|
sr_dbg("Current trigger slope %s", devc->trigger_slope);
|
|
|
|
|
|
|
|
return SR_OK;
|
|
|
|
}
|