560 lines
13 KiB
C
560 lines
13 KiB
C
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/*
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Copyright (c) 2010 Sven Peter <sven@fail0verflow.com>
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Copyright (c) 2010 Haxx Enterprises <bushing@gmail.com>
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All rights reserved.
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Redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following
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conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include "analyzer.h"
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#include "gl_usb.h"
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enum {
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HARD_DATA_CHECK_SUM = 0x00,
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PASS_WORD,
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DEVICE_ID0 = 0x10,
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DEVICE_ID1,
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START_STATUS = 0x20,
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DEVICE_STATUS = 0x21,
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FREQUENCY_REG0 = 0x30,
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FREQUENCY_REG1,
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FREQUENCY_REG2,
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FREQUENCY_REG3,
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FREQUENCY_REG4,
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MEMORY_LENGTH,
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CLOCK_SOURCE,
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TRIGGER_STATUS0 = 0x40,
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TRIGGER_STATUS1,
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TRIGGER_STATUS2,
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TRIGGER_STATUS3,
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TRIGGER_STATUS4,
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TRIGGER_STATUS5,
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TRIGGER_STATUS6,
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TRIGGER_STATUS7,
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TRIGGER_STATUS8,
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TRIGGER_COUNT0 = 0x50,
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TRIGGER_COUNT1,
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TRIGGER_LEVEL0 = 0x55,
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TRIGGER_LEVEL1,
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TRIGGER_LEVEL2,
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TRIGGER_LEVEL3,
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RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
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RAMSIZE_TRIGGERBAR_ADDRESS1,
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RAMSIZE_TRIGGERBAR_ADDRESS2,
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TRIGGERBAR_ADDRESS0,
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TRIGGERBAR_ADDRESS1,
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TRIGGERBAR_ADDRESS2,
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DONT_CARE_TRIGGERBAR,
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FILTER_ENABLE = 0x70,
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FILTER_STATUS,
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ENABLE_DELAY_TIME0 = 0x7A,
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ENABLE_DELAY_TIME1,
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ENABLE_INSERT_DATA0 = 0x80,
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ENABLE_INSERT_DATA1,
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ENABLE_INSERT_DATA2,
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ENABLE_INSERT_DATA3,
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COMPRESSION_TYPE0,
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COMPRESSION_TYPE1,
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TRIGGER_ADDRESS0 = 0x90,
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TRIGGER_ADDRESS1,
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TRIGGER_ADDRESS2,
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NOW_ADDRESS0 = 0x96,
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NOW_ADDRESS1,
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NOW_ADDRESS2,
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STOP_ADDRESS0 = 0x9B,
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STOP_ADDRESS1,
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STOP_ADDRESS2,
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READ_RAM_STATUS = 0xA0
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};
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static int g_trigger_status[9] = {0};
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static int g_trigger_count = 1;
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static int g_filter_status[8] = {0};
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static int g_filter_enable = 0;
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static int g_freq_value = 100;
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static int g_freq_scale = FREQ_SCALE_MHZ;
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static int g_memory_size = MEMORY_SIZE_512K;
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static int g_ramsize_triggerbar_addr = 0x80000>>2;
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static int g_triggerbar_addr = 0x3fe;
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static int g_compression = COMPRESSION_NONE;
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// maybe unk specifies an "endpoint" or "register" of sorts
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static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk, unsigned char flags)
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{
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assert(unk <= 3);
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return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
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}
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static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
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{
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int reg0=0, divisor=0, reg2=0;
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switch (scale) {
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case FREQ_SCALE_MHZ: // MHz
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if (freq >= 100 && freq <= 200) {
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reg0 = freq * 0.1;
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divisor = 1;
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reg2 = 0;
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break;
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}
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if (freq >= 50 && freq < 100) {
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reg0 = freq * 0.2;
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divisor = 2;
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reg2 = 0;
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break;
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}
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if (freq >= 10 && freq < 50) {
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if (freq == 25) {
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reg0 = 25;
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divisor = 5;
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reg2 = 1;
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break;
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} else {
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reg0 = freq * 0.5;
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divisor = 5;
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reg2 = 1;
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break;
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}
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}
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if (freq >= 2 && freq < 10) {
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divisor = 5;
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reg0 = freq * 2;
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reg2 = 2;
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break;
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}
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if (freq == 1) {
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divisor = 5;
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reg2 = 16;
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reg0 = 5;
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break;
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}
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divisor = 5;
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reg0 = 5;
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reg2 = 64;
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break;
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case FREQ_SCALE_HZ: // Hz
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if (freq >= 500 && freq < 1000) {
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reg0 = freq * 0.01;
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divisor = 10;
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reg2 = 64;
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break;
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}
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if (freq >= 300 && freq < 500) {
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reg0 = freq * 0.005 * 8;
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divisor = 5;
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reg2 = 67;
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break;
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}
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if (freq >= 100 && freq < 300) {
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reg0 = freq * 0.005 * 16;
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divisor = 5;
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reg2 = 68;
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break;
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}
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divisor = 5;
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reg0 = 5;
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reg2 = 64;
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break;
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case FREQ_SCALE_KHZ: // KHz
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if (freq >= 500 && freq < 1000) {
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reg0 = freq * 0.01;
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divisor = 5;
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reg2 = 17;
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break;
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}
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if (freq >= 100 && freq < 500) {
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reg0 = freq * 0.05;
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divisor = 5;
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reg2 = 32;
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break;
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}
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if (freq >= 50 && freq < 100) {
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reg0 = freq * 0.1;
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divisor = 5;
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reg2 = 33;
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break;
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}
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if (freq >= 10 && freq < 50) {
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if (freq == 25) {
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reg0 = 25;
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divisor = 5;
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reg2 = 49;
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break;
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}
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reg0 = freq * 0.5;
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divisor = 5;
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reg2 = 48;
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break;
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}
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if (freq >= 2 && freq < 10) {
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divisor = 5;
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reg0 = freq * 2;
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reg2 = 50;
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break;
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}
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divisor = 5;
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reg0 = 5;
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reg2 = 64;
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break;
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default:
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divisor = 5;
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reg0 = 5;
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reg2 = 64;
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break;
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}
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if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
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return -1; // divisor maybe?
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if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
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return -1; // 10 / 0.2
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if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
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return -1; // always 2
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if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
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return -1;
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return 0;
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}
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static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh, unsigned int address)
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{
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gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
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gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
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gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
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}
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static void __analyzer_set_triggerbar_address(libusb_device_handle *devh, unsigned int address)
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{
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gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
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gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
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gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
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}
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static void __analyzer_set_compression(libusb_device_handle *devh, unsigned int type)
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{
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gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
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gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
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}
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static void __analyzer_set_trigger_count(libusb_device_handle *devh, unsigned int count)
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{
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gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
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gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
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}
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static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
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{
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gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
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gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
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gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
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gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
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}
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static void analyzer_set_filter(libusb_device_handle *devh)
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{
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int i;
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gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
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for (i = 0; i < 8; i++)
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gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
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}
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void analyzer_reset(libusb_device_handle *devh)
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{
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analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
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analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
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}
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void analyzer_initialize(libusb_device_handle *devh)
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{
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analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
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analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
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analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
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}
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void analyzer_wait(libusb_device_handle *devh, int set, int unset)
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{
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int status;
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while(1) {
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status = gl_reg_read(devh, DEVICE_STATUS);
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if ((status & set) && ((status & unset) == 0))
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return;
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}
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}
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void analyzer_read_start(libusb_device_handle *devh)
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{
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int i;
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analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);
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for (i = 0; i < 8; i++)
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(void)gl_reg_read(devh, READ_RAM_STATUS);
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}
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int analyzer_read_data(libusb_device_handle *devh, void *buffer, unsigned int size)
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{
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return gl_read_bulk(devh, buffer, size);
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}
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void analyzer_read_stop(libusb_device_handle *devh)
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{
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analyzer_write_status(devh, 3, STATUS_FLAG_20);
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analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
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}
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void analyzer_start(libusb_device_handle *devh)
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{
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analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
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analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
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analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
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analyzer_write_status(devh, 1, STATUS_FLAG_GO);
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}
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void analyzer_configure(libusb_device_handle *devh)
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{
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// Write_Start_Status
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analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
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analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
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// Start_Config_Outside_Device ?
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analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
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analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
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//SetData_To_Frequence_Reg
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__analyzer_set_freq(devh, g_freq_value, g_freq_scale);
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//SetMemory_Length
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gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
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//Sele_Inside_Outside_Clock
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gl_reg_write(devh, CLOCK_SOURCE, 0x03);
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//Set_Trigger_Status
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int i;
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for (i = 0; i < 9; i++)
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gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
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||
|
|
__analyzer_set_trigger_count(devh, g_trigger_count);
|
||
|
|
|
||
|
|
//Set_Trigger_Level
|
||
|
|
gl_reg_write(devh, TRIGGER_LEVEL0, 0x31);
|
||
|
|
gl_reg_write(devh, TRIGGER_LEVEL1, 0x31);
|
||
|
|
gl_reg_write(devh, TRIGGER_LEVEL2, 0x31);
|
||
|
|
gl_reg_write(devh, TRIGGER_LEVEL3, 0x31);
|
||
|
|
|
||
|
|
__analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr); // size of actual memory >> 2
|
||
|
|
__analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
|
||
|
|
|
||
|
|
//Set_Dont_Care_TriggerBar
|
||
|
|
gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
|
||
|
|
|
||
|
|
//Enable_Status
|
||
|
|
analyzer_set_filter(devh);
|
||
|
|
|
||
|
|
//Set_Enable_Delay_Time
|
||
|
|
gl_reg_write(devh, 0x7a, 0x00);
|
||
|
|
gl_reg_write(devh, 0x7b, 0x00);
|
||
|
|
analyzer_write_enable_insert_data(devh);
|
||
|
|
__analyzer_set_compression(devh,g_compression);
|
||
|
|
}
|
||
|
|
|
||
|
|
void analyzer_add_trigger(int channel, int type)
|
||
|
|
{
|
||
|
|
if ((channel & 0xf) >= 8)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (type == TRIGGER_HIGH || type == TRIGGER_LOW) {
|
||
|
|
int i;
|
||
|
|
if (channel & CHANNEL_A)
|
||
|
|
i = 0;
|
||
|
|
else if (channel & CHANNEL_B)
|
||
|
|
i = 2;
|
||
|
|
else if (channel & CHANNEL_C)
|
||
|
|
i = 4;
|
||
|
|
else if (channel & CHANNEL_D)
|
||
|
|
i = 6;
|
||
|
|
else
|
||
|
|
return;
|
||
|
|
if ((channel & 0xf) >= 4) {
|
||
|
|
i++;
|
||
|
|
channel -= 4;
|
||
|
|
}
|
||
|
|
g_trigger_status[i] |= 1 << ((2 * channel) + (type == TRIGGER_LOW ? 1 : 0));
|
||
|
|
} else {
|
||
|
|
if (type == TRIGGER_POSEDGE)
|
||
|
|
g_trigger_status[8] = 0x40;
|
||
|
|
else if(type == TRIGGER_NEGEDGE)
|
||
|
|
g_trigger_status[8] = 0x80;
|
||
|
|
else
|
||
|
|
g_trigger_status[8] = 0xc0;
|
||
|
|
|
||
|
|
// FIXME: just guessed the index; need to verify
|
||
|
|
if (channel & CHANNEL_B)
|
||
|
|
g_trigger_status[8] += 8;
|
||
|
|
else if (channel & CHANNEL_C)
|
||
|
|
g_trigger_status[8] += 16;
|
||
|
|
else if (channel & CHANNEL_D)
|
||
|
|
g_trigger_status[8] += 24;
|
||
|
|
g_trigger_status[8] += channel % 8;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void analyzer_add_filter(int channel, int type)
|
||
|
|
{
|
||
|
|
if (type != FILTER_HIGH && type != FILTER_LOW)
|
||
|
|
return;
|
||
|
|
if ((channel & 0xf) >= 8)
|
||
|
|
return;
|
||
|
|
|
||
|
|
int i;
|
||
|
|
if (channel & CHANNEL_A)
|
||
|
|
i = 0;
|
||
|
|
else if (channel & CHANNEL_B)
|
||
|
|
i = 2;
|
||
|
|
else if (channel & CHANNEL_C)
|
||
|
|
i = 4;
|
||
|
|
else if (channel & CHANNEL_D)
|
||
|
|
i = 6;
|
||
|
|
else
|
||
|
|
return;
|
||
|
|
if ((channel & 0xf) >= 4) {
|
||
|
|
i++;
|
||
|
|
channel -= 4;
|
||
|
|
}
|
||
|
|
g_filter_status[i] |= 1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
|
||
|
|
g_filter_enable = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
void analyzer_set_trigger_count(int count)
|
||
|
|
{
|
||
|
|
g_trigger_count = count;
|
||
|
|
}
|
||
|
|
|
||
|
|
void analyzer_set_freq(int freq, int scale)
|
||
|
|
{
|
||
|
|
g_freq_value = freq;
|
||
|
|
g_freq_scale = scale;
|
||
|
|
}
|
||
|
|
|
||
|
|
void analyzer_set_memory_size(unsigned int size)
|
||
|
|
{
|
||
|
|
g_memory_size = size;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void analyzer_set_ramsize_trigger_address(unsigned int address)
|
||
|
|
{
|
||
|
|
g_ramsize_triggerbar_addr = address;
|
||
|
|
}
|
||
|
|
|
||
|
|
void analyzer_set_triggerbar_address(unsigned int address)
|
||
|
|
{
|
||
|
|
g_triggerbar_addr = address;
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned int analyzer_read_id(libusb_device_handle *devh)
|
||
|
|
{
|
||
|
|
return gl_reg_read(devh, DEVICE_ID1) << 8 | gl_reg_read(devh, DEVICE_ID0);
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
|
||
|
|
{
|
||
|
|
return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh, STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned int analyzer_get_now_address(libusb_device_handle *devh)
|
||
|
|
{
|
||
|
|
return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh, NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
|
||
|
|
{
|
||
|
|
return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh, TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
|
||
|
|
}
|
||
|
|
|
||
|
|
void analyzer_set_compression(unsigned int type)
|
||
|
|
{
|
||
|
|
g_compression = type;
|
||
|
|
}
|
||
|
|
|
||
|
|
void analyzer_wait_button(libusb_device_handle *devh)
|
||
|
|
{
|
||
|
|
analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
void analyzer_wait_data(libusb_device_handle *devh)
|
||
|
|
{
|
||
|
|
analyzer_wait(devh, STATUS_READY | 8, STATUS_BUSY);
|
||
|
|
}
|
||
|
|
|
||
|
|
int analyzer_decompress(void *input, unsigned int input_len, void *output, unsigned int output_len)
|
||
|
|
{
|
||
|
|
unsigned char *in = input;
|
||
|
|
unsigned char *out = output;
|
||
|
|
unsigned int A, B, C, count;
|
||
|
|
unsigned int written = 0;
|
||
|
|
|
||
|
|
while (input_len > 0) {
|
||
|
|
A = *in++;
|
||
|
|
B = *in++;
|
||
|
|
C = *in++;
|
||
|
|
count = (*in++) + 1;
|
||
|
|
|
||
|
|
if (count > output_len)
|
||
|
|
count = output_len;
|
||
|
|
output_len -= count;
|
||
|
|
written += count;
|
||
|
|
|
||
|
|
while (count--) {
|
||
|
|
*out++ = A;
|
||
|
|
*out++ = B;
|
||
|
|
*out++ = C;
|
||
|
|
*out++ = 0; // channel D
|
||
|
|
}
|
||
|
|
|
||
|
|
input_len -= 4;
|
||
|
|
if (output_len == 0)
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
return written;
|
||
|
|
}
|