Rewrote the trigger config. Added trigger position and trigger slope
This commit is contained in:
lelazary
Uwe Hermann
parent
5a24e89ca4
commit
087a9161ff
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@ -22,6 +22,8 @@
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static const int hwcaps[] = {
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SR_HWCAP_LOGIC_ANALYZER,
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SR_HWCAP_SAMPLERATE,
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SR_HWCAP_TRIGGER_SLOPE,
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SR_HWCAP_HORIZ_TRIGGERPOS,
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// SR_HWCAP_CAPTURE_RATIO,
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SR_HWCAP_LIMIT_SAMPLES,
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// SR_HWCAP_RLE,
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@ -326,6 +328,9 @@ static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
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{
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int ret;
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struct dev_context *devc;
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devc = sdi->priv;
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if (sdi->status != SR_ST_ACTIVE)
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return SR_ERR;
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@ -340,6 +345,34 @@ static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
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case SR_HWCAP_CAPTURE_RATIO:
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ret = SR_OK;
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break;
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case SR_HWCAP_TRIGGER_SLOPE:
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{
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uint64_t slope = *(const uint64_t *)value;
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if (slope != SLOPE_NEGATIVE && slope != SLOPE_POSITIVE)
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{
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sr_err("Invalid trigger slope");
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ret = SR_ERR_ARG;
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} else {
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devc->trigger_slope = slope;
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ret = SR_OK;
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}
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}
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break;
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case SR_HWCAP_HORIZ_TRIGGERPOS:
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{
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float pos = *(const float *)value;
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if (pos < 0 || pos > 255) {
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sr_err("Trigger position (%f) should be between 0 and 255.", pos);
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ret = SR_ERR_ARG;
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} else {
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int trigger_pos = (int)pos;
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printf("Set trigger posion to %X\n", trigger_pos&0xff);
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devc->trigger_holdoff[0] = trigger_pos&0xff;
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ret = SR_OK;
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}
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}
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break;
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case SR_HWCAP_RLE:
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ret = SR_OK;
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break;
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@ -371,20 +404,6 @@ static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
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return SR_ERR;
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}
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/*
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* Enable/disable channel groups in the flag register according to the
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* probe mask. Calculate this here, because num_channels is needed
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* to limit readcount.
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*/
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//changrp_mask = 0;
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//num_channels = 0;
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//for (i = 0; i < 4; i++) {
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// if (devc->probe_mask & (0xff << (i * 8))) {
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// changrp_mask |= (1 << i);
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// num_channels++;
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// }
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//}
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/* FIXME: No need to do full reconfigure every time */
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// ret = mso_reset_fsm(sdi);
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// if (ret != SR_OK)
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@ -410,26 +429,17 @@ static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
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if (ret != SR_OK)
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return ret;
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printf("Configure trigger\n");
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ret = mso_configure_trigger(sdi);
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if (ret != SR_OK)
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return ret;
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/* FIXME: trigger_position */
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/* END of config hardware part */
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/* with trigger */
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printf("arm\n");
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ret = mso_arm(sdi);
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if (ret != SR_OK)
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return ret;
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/* without trigger */
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// ret = mso_force_capture(sdi);
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// if (ret != SR_OK)
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// return ret;
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ret = mso_arm(sdi);
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if (ret != SR_OK)
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return ret;
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/* Start acquisition on the device. */
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printf("Check trigger\n");
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@ -471,7 +481,7 @@ static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
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return SR_OK;
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}
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/* TODO: This stops acquisition on ALL devices, ignoring dev_index. */
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/* This stops acquisition on ALL devices, ignoring dev_index. */
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static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
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{
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/* Avoid compiler warnings. */
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@ -70,71 +70,73 @@ ret:
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SR_PRIV int mso_configure_trigger(struct sr_dev_inst *sdi)
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{
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struct dev_context *devc = sdi->priv;
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uint16_t ops[16];
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uint16_t dso_trigger = mso_calc_raw_from_mv(devc);
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uint16_t threshold_value = mso_calc_raw_from_mv(devc);
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dso_trigger &= 0x3ff;
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if ((!devc->trigger_slope && devc->trigger_chan == 1) ||
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(devc->trigger_slope &&
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(devc->trigger_chan == 0 ||
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devc->trigger_chan == 2 ||
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devc->trigger_chan == 3)))
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dso_trigger |= 0x400;
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switch (devc->trigger_chan) {
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case 1:
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dso_trigger |= 0xe000;
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case 2:
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dso_trigger |= 0x4000;
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break;
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case 3:
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dso_trigger |= 0x2000;
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break;
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case 4:
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dso_trigger |= 0xa000;
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break;
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case 5:
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dso_trigger |= 0x8000;
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break;
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default:
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case 0:
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break;
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}
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threshold_value = 0x153C;
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uint8_t trigger_config = 0;
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if (devc->trigger_slope)
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trigger_config |= 0x04; //Trigger on falling edge
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switch (devc->trigger_outsrc) {
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case 1:
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dso_trigger |= 0x800;
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trigger_config |= 0x00; //Trigger pulse output
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break;
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case 2:
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dso_trigger |= 0x1000;
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trigger_config |= 0x08; //PWM DAC from the pattern generator buffer
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break;
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case 3:
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dso_trigger |= 0x1800;
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trigger_config |= 0x18; //White noise
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break;
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}
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ops[0] = mso_trans(5, devc->la_trigger);
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ops[1] = mso_trans(6, devc->la_trigger_mask);
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ops[2] = mso_trans(3, dso_trigger & 0xff);
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ops[3] = mso_trans(4, (dso_trigger >> 8) & 0xff);
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ops[4] = mso_trans(11,
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switch (devc->trigger_chan) {
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case 0:
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trigger_config |= 0x00; //DSO level trigger //b00000000
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break;
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case 1:
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trigger_config |= 0x20; //DSO level trigger & width < trigger_width
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break;
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case 2:
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trigger_config |= 0x40; //DSO level trigger & width >= trigger_width
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break;
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case 3:
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trigger_config |= 0x60; //LA combination trigger
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break;
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}
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//Last bit of trigger config reg 4 needs to be 1 for trigger enable,
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//otherwise the trigger is not enabled
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if (devc->use_trigger)
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trigger_config |= 0x80;
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uint16_t ops[18];
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ops[0] = mso_trans(3, threshold_value & 0xff);
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//The trigger_config also holds the 2 MSB bits from the threshold value
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ops[1] = mso_trans(4, trigger_config | (threshold_value >> 8) & 0x03);
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ops[2] = mso_trans(5, devc->la_trigger);
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ops[3] = mso_trans(6, devc->la_trigger_mask);
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ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
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ops[5] = mso_trans(8, devc->trigger_holdoff[1]);
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ops[6] = mso_trans(11,
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devc->dso_trigger_width / SR_HZ_TO_NS(devc->cur_rate));
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/* Select the SPI/I2C trigger config bank */
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ops[5] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
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ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
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/* Configure the SPI/I2C protocol trigger */
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ops[6] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
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ops[7] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
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ops[8] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
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ops[9] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
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ops[10] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
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ops[11] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
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ops[12] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
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ops[13] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
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ops[14] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
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ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
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ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
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ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
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ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
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ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
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ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
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ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
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ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
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ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
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/* Select the default config bank */
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ops[15] = mso_trans(REG_CTL2, devc->ctlbase2);
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ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);
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return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
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}
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@ -335,13 +337,11 @@ SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info)
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int ret;
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sr_dbg("Requesting trigger state.");
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printf("Send Controll message\n");
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ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
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if (info == NULL || ret != SR_OK)
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return ret;
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printf("REad buffer\n");
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uint8_t buf = 0;
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if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
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ret = SR_ERR;
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@ -387,9 +387,9 @@ SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
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* to read the data */
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if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
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devc->trigger_state = in[0];
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printf("Got %c for trigger \n", in[0]);
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//printf("Got %c for trigger \n", in[0]);
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if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
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printf("Trigger is ready %c\n", MSO_TRIGGER_DATAREADY);
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//printf("Trigger is ready %c\n", MSO_TRIGGER_DATAREADY);
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mso_read_buffer(sdi);
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devc->buffer_n = 0;
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} else {
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@ -450,59 +450,42 @@ SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
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SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi)
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{
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struct dev_context *devc;
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struct sr_probe *probe;
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GSList *l;
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int probe_bit, stage, i;
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char *tc;
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/*
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devc = sdi->priv;
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for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
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devc->la_trigger_mask[i] = 0;
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devc->la_trigger[i] = 0;
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}
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stage = -1;
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devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
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devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode).
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devc->dso_trigger_voltage = 3;
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devc->dso_probe_attn = 1;
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devc->trigger_outsrc = 0;
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devc->trigger_chan = 3; //LA combination trigger
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devc->use_trigger = FALSE;
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for (l = sdi->probes; l; l = l->next) {
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probe = (struct sr_probe *)l->data;
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if (probe->enabled == FALSE)
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continue;
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//if (probe->index > 7)
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// devc->sample_wide = TRUE;
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probe_bit = 1 << (probe->index);
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int probe_bit = 1 << (probe->index);
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if (!(probe->trigger))
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continue;
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devc->use_trigger = TRUE;
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//Configure trigger mask and value.
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stage = 0;
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for (tc = probe->trigger; *tc; tc++) {
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devc->trigger_mask[stage] |= probe_bit;
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if (*tc == '1')
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devc->trigger_value[stage] |= probe_bit;
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stage++;
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if (stage > NUM_TRIGGER_STAGES)
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return SR_ERR;
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}
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}
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*/
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//if (stage == -1)
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// /*
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// * We didn't configure any triggers, make sure acquisition
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// * doesn't wait for any.
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// */
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// devc->trigger_stage = TRIGGER_FIRED;
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//else
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// devc->trigger_stage = 0;
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devc->la_trigger_mask &= ~probe_bit;
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if (*tc == '1')
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devc->la_trigger |= probe_bit;
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}
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}
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return SR_OK;
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}
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@ -40,7 +40,7 @@
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#define NUM_PROBES 8
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#define NUM_TRIGGER_STAGES 4
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#define TRIGGER_TYPES "01"
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#define TRIGGER_TYPES "01" //the first r/f is used for the whole group
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#define SERIALCOMM "460800/8n1/flow=2"
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#define SERIALCONN "/dev/ttyUSB0"
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#define CLOCK_RATE SR_MHZ(100)
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@ -54,6 +54,11 @@
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#define MSO_TRIGGER_FIRED '5'
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#define MSO_TRIGGER_DATAREADY '6'
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enum trigger_slopes {
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SLOPE_POSITIVE = 0,
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SLOPE_NEGATIVE,
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};
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/* Structure for the pattern generator state */
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struct mso_patgen {
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/* Pattern generator clock config */
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@ -102,10 +107,12 @@ struct dev_context {
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uint8_t la_threshold;
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uint64_t cur_rate;
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uint8_t dso_probe_attn;
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int8_t use_trigger;
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uint8_t trigger_chan;
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uint8_t trigger_slope;
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uint8_t trigger_outsrc;
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uint8_t trigger_state;
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uint8_t trigger_holdoff[2];
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uint8_t la_trigger;
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uint8_t la_trigger_mask;
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double dso_trigger_voltage;
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