saleae-logic16: Initialize the FPGA.
The map_eeprom_data function is currently unknown. The map entries provided were observed via bus-snooping of the vendor software on my device. Other devices may need additional values.
This commit is contained in:
Marcus Comstedt
Uwe Hermann
parent
5eea4305ad
commit
15abcf0f58
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@ -271,6 +271,11 @@ static int logic16_dev_open(struct sr_dev_inst *sdi)
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break;
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}
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if ((ret = saleae_logic16_init_device(sdi)) != SR_OK) {
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sr_err("Failed to init device.");
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break;
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}
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sdi->status = SR_ST_ACTIVE;
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sr_info("Opened device %d on %d.%d, "
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"interface %d.",
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@ -19,6 +19,422 @@
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#include "protocol.h"
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#include <stdint.h>
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#include <string.h>
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#include <glib.h>
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#include <glib/gstdio.h>
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#include <stdio.h>
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#include <errno.h>
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#include <math.h>
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#include "libsigrok.h"
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#include "libsigrok-internal.h"
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#define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream"
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#define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream"
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#define COMMAND_START_ACQUISITION 1
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#define COMMAND_ABORT_ACQUISITION_ASYNC 2
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#define COMMAND_WRITE_EEPROM 6
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#define COMMAND_READ_EEPROM 7
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#define COMMAND_WRITE_LED_TABLE 0x7a
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#define COMMAND_SET_LED_MODE 0x7b
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#define COMMAND_RETURN_TO_BOOTLOADER 0x7c
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#define COMMAND_ABORT_ACQUISITION_SYNC 0x7d
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#define COMMAND_FPGA_UPLOAD_INIT 0x7e
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#define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f
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#define COMMAND_FPGA_WRITE_REGISTER 0x80
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#define COMMAND_FPGA_READ_REGISTER 0x81
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#define COMMAND_GET_REVID 0x82
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#define WRITE_EEPROM_COOKIE1 0x42
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#define WRITE_EEPROM_COOKIE2 0x55
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#define READ_EEPROM_COOKIE1 0x33
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#define READ_EEPROM_COOKIE2 0x81
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#define ABORT_ACQUISITION_SYNC_PATTERN 0x55
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static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
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{
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uint8_t state1 = 0x9b, state2 = 0x54;
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int i;
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for (i=0; i<cnt; i++) {
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uint8_t t, v = src[i];
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t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39;
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t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45;
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dest[i] = state2 = t;
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state1 = v;
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}
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}
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static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
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{
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uint8_t state1 = 0x9b, state2 = 0x54;
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int i;
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for (i=0; i<cnt; i++) {
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uint8_t t, v = src[i];
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t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1;
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t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2;
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dest[i] = state1 = t;
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state2 = v;
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}
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}
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static int do_ep1_command(const struct sr_dev_inst *sdi,
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const uint8_t *command, uint8_t cmd_len,
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uint8_t *reply, uint8_t reply_len)
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{
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uint8_t buf[64];
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struct sr_usb_dev_inst *usb;
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int ret, xfer;
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usb = sdi->conn;
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if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 ||
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command == NULL || (reply_len > 0 && reply == NULL))
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return SR_ERR_ARG;
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encrypt(buf, command, cmd_len);
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ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000);
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if (ret != 0) {
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sr_dbg("Failed to send EP1 command 0x%02x: %s",
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command[0], libusb_error_name(ret));
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return SR_ERR;
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}
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if (xfer != cmd_len) {
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sr_dbg("Failed to send EP1 command 0x%02x: incorrect length %d != %d",
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xfer, cmd_len);
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return SR_ERR;
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}
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if (reply_len == 0)
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return SR_OK;
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ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len, &xfer, 1000);
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if (ret != 0) {
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sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s",
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command[0], libusb_error_name(ret));
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return SR_ERR;
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}
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if (xfer != reply_len) {
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sr_dbg("Failed to receive reply to EP1 command 0x%02x: incorrect length %d != %d",
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xfer, reply_len);
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return SR_ERR;
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}
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decrypt(reply, buf, reply_len);
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return SR_OK;
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}
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static int read_eeprom(const struct sr_dev_inst *sdi,
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uint8_t address, uint8_t length, uint8_t *buf)
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{
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uint8_t command[5] = {
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COMMAND_READ_EEPROM,
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READ_EEPROM_COOKIE1,
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READ_EEPROM_COOKIE2,
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address,
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length,
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};
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return do_ep1_command(sdi, command, 5, buf, length);
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}
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static int upload_led_table(const struct sr_dev_inst *sdi,
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const uint8_t *table, uint8_t offset, uint8_t cnt)
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{
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uint8_t command[64];
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int ret;
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if (cnt < 1 || cnt+offset > 64 || table == NULL)
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return SR_ERR_ARG;
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while (cnt > 0) {
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uint8_t chunk = (cnt > 32? 32 : cnt);
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command[0] = COMMAND_WRITE_LED_TABLE;
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command[1] = offset;
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command[2] = chunk;
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memcpy(command+3, table, chunk);
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if ((ret = do_ep1_command(sdi, command, 3+chunk, NULL, 0)) != SR_OK)
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return ret;
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table += chunk;
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offset += chunk;
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cnt -= chunk;
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}
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return SR_OK;
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}
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static int set_led_mode(const struct sr_dev_inst *sdi,
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uint8_t animate, uint16_t t2reload, uint8_t div,
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uint8_t repeat)
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{
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uint8_t command[6] = {
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COMMAND_SET_LED_MODE,
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animate,
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t2reload&0xff,
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t2reload>>8,
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div,
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repeat,
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};
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return do_ep1_command(sdi, command, 6, NULL, 0);
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}
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static int read_fpga_register(const struct sr_dev_inst *sdi,
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uint8_t address, uint8_t *value)
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{
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uint8_t command[3] = {
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COMMAND_FPGA_READ_REGISTER,
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1,
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address,
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};
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return do_ep1_command(sdi, command, 3, value, 1);
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}
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static int write_fpga_registers(const struct sr_dev_inst *sdi,
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uint8_t (*regs)[2], uint8_t cnt)
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{
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uint8_t command[64];
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int i;
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if (cnt < 1 || cnt > 31)
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return SR_ERR_ARG;
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command[0] = COMMAND_FPGA_WRITE_REGISTER;
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command[1] = cnt;
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for (i=0; i<cnt; i++) {
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command[2+2*i] = regs[i][0];
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command[3+2*i] = regs[i][1];
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}
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return do_ep1_command(sdi, command, 2*(cnt+1), NULL, 0);
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}
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static int write_fpga_register(const struct sr_dev_inst *sdi,
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uint8_t address, uint8_t value)
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{
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uint8_t regs[2] = { address, value };
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return write_fpga_registers(sdi, ®s, 1);
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}
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static uint8_t map_eeprom_data(uint8_t v)
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{
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/* ??? */
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switch (v) {
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case 0x00: return 0x7a;
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case 0x01: return 0x79;
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case 0x05: return 0x85;
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case 0x10: return 0x6a;
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case 0x11: return 0x69;
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case 0x14: return 0x76;
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case 0x15: return 0x75;
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case 0x41: return 0x39;
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case 0x50: return 0x2a;
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case 0x51: return 0x29;
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case 0x55: return 0x35;
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default:
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sr_err("No mapping of 0x%02x defined", v);
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return 0xff;
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}
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}
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static int prime_fpga(const struct sr_dev_inst *sdi)
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{
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uint8_t eeprom_data[16];
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uint8_t old_reg_10, status;
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uint8_t regs[8][2] = {
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{10, 0x00},
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{10, 0x40},
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{12, 0},
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{10, 0xc0},
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{10, 0x40},
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{ 6, 0},
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{ 7, 1},
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{ 7, 0}
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};
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int i, ret;
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if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK)
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return ret;
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if ((ret = read_fpga_register(sdi, 10, &old_reg_10)) != SR_OK)
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return ret;
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for (i=0; i<16; i++) {
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regs[2][1] = eeprom_data[i];
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regs[5][1] = map_eeprom_data(eeprom_data[i]);
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if (i)
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ret = write_fpga_registers(sdi, ®s[2], 6);
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else
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ret = write_fpga_registers(sdi, ®s[0], 8);
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if (ret != SR_OK)
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return ret;
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}
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if ((ret = write_fpga_register(sdi, 10, old_reg_10)) != SR_OK)
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return ret;
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if ((ret = read_fpga_register(sdi, 0, &status)) != SR_OK)
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return ret;
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if (status != 0x10) {
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sr_err("Invalid FPGA status: 0x%02x != 0x10", status);
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return SR_ERR;
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}
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return SR_OK;
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}
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static void make_heartbeat(uint8_t *table, int len)
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{
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int i, j;
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memset(table, 0, len);
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len >>= 3;
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for (i=0; i<2; i++)
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for (j=0; j<len; j++)
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*table++ = sin(j*M_PI/len)*255;
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}
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static int configure_led(const struct sr_dev_inst *sdi)
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{
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uint8_t table[64];
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int ret;
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make_heartbeat(table, 64);
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if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK)
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return ret;
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return set_led_mode(sdi, 1, 6250, 0, 1);
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}
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static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
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enum voltage_range vrange)
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{
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struct dev_context *devc;
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int offset, chunksize, ret;
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const char *filename;
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FILE *fw;
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unsigned char buf[256*62];
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devc = sdi->priv;
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if (devc->cur_voltage_range == vrange)
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return SR_OK;
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switch (vrange) {
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case VOLTAGE_RANGE_18_33_V:
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filename = FPGA_FIRMWARE_18;
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break;
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case VOLTAGE_RANGE_5_V:
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filename = FPGA_FIRMWARE_33;
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break;
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default:
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sr_err("Unsupported voltage range");
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return SR_ERR;
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}
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sr_info("Uploading FPGA bitstream at %s", filename);
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if ((fw = g_fopen(filename, "rb")) == NULL) {
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sr_err("Unable to open bitstream file %s for reading: %s",
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filename, strerror(errno));
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return SR_ERR;
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}
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buf[0] = COMMAND_FPGA_UPLOAD_INIT;
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if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) {
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fclose(fw);
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return ret;
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}
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while (1) {
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chunksize = fread(buf, 1, sizeof(buf), fw);
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if (chunksize == 0)
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break;
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for (offset = 0; offset < chunksize; offset += 62) {
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uint8_t command[64];
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uint8_t len = (offset + 62 > chunksize?
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chunksize - offset : 62);
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command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
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command[1] = len;
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memcpy(command+2, buf+offset, len);
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if ((ret = do_ep1_command(sdi, command, len+2, NULL, 0)) != SR_OK) {
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fclose(fw);
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return ret;
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}
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}
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sr_info("Uploaded %d bytes", chunksize);
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}
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fclose(fw);
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sr_info("FPGA bitstream upload done");
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if ((ret = prime_fpga(sdi)) != SR_OK)
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return ret;
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if ((ret = configure_led(sdi)) != SR_OK)
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return ret;
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/* XXX */
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if ((ret = configure_led(sdi)) != SR_OK)
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return ret;
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devc->cur_voltage_range = vrange;
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return SR_OK;
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}
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SR_PRIV int saleae_logic16_abort_acquisition(const struct sr_dev_inst *sdi)
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{
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static const uint8_t command[2] = {
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COMMAND_ABORT_ACQUISITION_SYNC,
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ABORT_ACQUISITION_SYNC_PATTERN,
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};
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uint8_t reply, expected_reply;
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int ret;
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if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK)
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return ret;
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expected_reply = ~command[1];
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if (reply != expected_reply) {
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sr_err("Invalid response for abort acquisition command: "
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"0x%02x != 0x%02x", reply, expected_reply);
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return SR_ERR;
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}
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return SR_OK;
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}
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SR_PRIV int saleae_logic16_init_device(const struct sr_dev_inst *sdi)
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{
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struct dev_context *devc;
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int ret;
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devc = sdi->priv;
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devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN;
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if ((ret = saleae_logic16_abort_acquisition(sdi)) != SR_OK)
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return ret;
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if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
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return ret;
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if ((ret = upload_fpga_bitstream(sdi, VOLTAGE_RANGE_18_33_V)) != SR_OK)
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return ret;
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return SR_OK;
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}
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SR_PRIV int saleae_logic16_receive_data(int fd, int revents, void *cb_data)
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{
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(void)fd;
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@ -34,6 +34,12 @@
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#define sr_warn(s, args...) sr_warn(LOG_PREFIX s, ## args)
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#define sr_err(s, args...) sr_err(LOG_PREFIX s, ## args)
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enum voltage_range {
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VOLTAGE_RANGE_UNKNOWN,
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VOLTAGE_RANGE_18_33_V, /* 1.8V and 3.3V logic */
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VOLTAGE_RANGE_5_V, /* 5V logic */
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};
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/** Private, per-device-instance driver context. */
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struct dev_context {
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/*
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@ -46,8 +52,18 @@ struct dev_context {
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/** The currently configured samplerate of the device. */
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uint64_t cur_samplerate;
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/** The currently configured input voltage of the device */
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enum voltage_range cur_voltage_range;
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/*
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* EEPROM data from address 8
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*/
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uint8_t eeprom_data[8];
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};
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SR_PRIV int saleae_logic16_abort_acquisition(const struct sr_dev_inst *sdi);
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SR_PRIV int saleae_logic16_init_device(const struct sr_dev_inst *sdi);
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SR_PRIV int saleae_logic16_receive_data(int fd, int revents, void *cb_data);
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#endif
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