added edge triggers
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1f9bcd0f94
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1e0de84608
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@ -501,6 +501,14 @@ static int set_trigger(const struct sr_dev_inst *sdi, int stage)
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if (write_longcommand(devc, cmd, arg) != SR_OK)
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return SR_ERR;
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cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
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arg[0] = devc->trigger_edge[stage] & 0xff;
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arg[1] = (devc->trigger_edge[stage] >> 8) & 0xff;
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arg[2] = (devc->trigger_edge[stage] >> 16) & 0xff;
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arg[3] = (devc->trigger_edge[stage] >> 24) & 0xff;
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if (write_longcommand(devc, cmd, arg) != SR_OK)
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return SR_ERR;
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return SR_OK;
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}
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@ -583,13 +591,13 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi,
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arg[1] = ((readcount - 1) & 0xff00) >> 8;
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arg[2] = ((readcount - 1) & 0xff0000) >> 16;
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arg[3] = ((readcount - 1) & 0xff000000) >> 24;
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if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK)
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if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK)
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return SR_ERR;
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arg[0] = ((delaycount - 1) & 0xff);
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arg[1] = ((delaycount - 1) & 0xff00) >> 8;
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arg[2] = ((delaycount - 1) & 0xff0000) >> 16;
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arg[3] = ((delaycount - 1) & 0xff000000) >> 24;
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if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK)
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if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK)
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return SR_ERR;
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/* Flag register. */
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sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
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@ -167,6 +167,7 @@ SR_PRIV int p_ols_configure_channels(const struct sr_dev_inst *sdi)
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for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
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devc->trigger_mask[i] = 0;
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devc->trigger_value[i] = 0;
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devc->trigger_edge[i] = 0;
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}
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devc->num_stages = 0;
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@ -194,8 +195,10 @@ SR_PRIV int p_ols_configure_channels(const struct sr_dev_inst *sdi)
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stage = 0;
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for (tc = ch->trigger; tc && *tc; tc++) {
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devc->trigger_mask[stage] |= channel_bit;
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if (*tc == '1')
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if ((*tc == '1') || (*tc == 'r'))
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devc->trigger_value[stage] |= channel_bit;
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if ((*tc == 'r') || (*tc == 'f'))
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devc->trigger_edge[stage] |= channel_bit;
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stage++;
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/* Only supporting parallel mode, with up to 4 stages. */
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if (stage > 3)
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@ -39,7 +39,7 @@
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#define NUM_CHANNELS 32
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#define NUM_TRIGGER_STAGES 4
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#define TRIGGER_TYPE "01"
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#define TRIGGER_TYPE "01rf"
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#define CLOCK_RATE SR_MHZ(100)
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#define MIN_NUM_SAMPLES 4
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#define DEFAULT_SAMPLERATE SR_MHZ(100)
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@ -57,6 +57,7 @@
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#define CMD_SET_TRIGGER_MASK 0xc0
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#define CMD_SET_TRIGGER_VALUE 0xc1
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#define CMD_SET_TRIGGER_CONFIG 0xc2
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#define CMD_SET_TRIGGER_EDGE 0xc3
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/* Trigger config */
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#define TRIGGER_START (1 << 3)
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@ -97,6 +98,7 @@ struct dev_context {
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uint32_t channel_mask;
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uint32_t trigger_mask[4];
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uint32_t trigger_value[4];
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uint32_t trigger_edge[4];
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int num_stages;
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uint16_t flag_reg;
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