dslogic: Refactored firmware selection into dslogic_fpga_firmware_upload
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adcb9951f8
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3566348b92
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@ -332,7 +332,6 @@ static int dev_open(struct sr_dev_inst *sdi)
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struct sr_dev_driver *di = sdi->driver;
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struct sr_usb_dev_inst *usb;
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struct dev_context *devc;
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const char *fpga_firmware = NULL;
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int ret;
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int64_t timediff_us, timediff_ms;
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@ -392,22 +391,8 @@ static int dev_open(struct sr_dev_inst *sdi)
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return SR_ERR;
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}
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if (!strcmp(devc->profile->model, "DSLogic")) {
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if (devc->voltage_threshold == DS_VOLTAGE_RANGE_18_33_V)
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fpga_firmware = DSLOGIC_FPGA_FIRMWARE_3V3;
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else
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fpga_firmware = DSLOGIC_FPGA_FIRMWARE_5V;
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} else if (!strcmp(devc->profile->model, "DSLogic Pro")){
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fpga_firmware = DSLOGIC_PRO_FPGA_FIRMWARE;
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} else if (!strcmp(devc->profile->model, "DSLogic Plus")){
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fpga_firmware = DSLOGIC_PLUS_FPGA_FIRMWARE;
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} else if (!strcmp(devc->profile->model, "DSLogic Basic")){
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fpga_firmware = DSLOGIC_BASIC_FPGA_FIRMWARE;
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} else if (!strcmp(devc->profile->model, "DSCope")) {
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fpga_firmware = DSCOPE_FPGA_FIRMWARE;
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}
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if ((ret = dslogic_fpga_firmware_upload(sdi, fpga_firmware)) != SR_OK)
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if ((ret = dslogic_fpga_firmware_upload(sdi)) != SR_OK)
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return ret;
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if (devc->cur_samplerate == 0) {
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@ -574,18 +559,7 @@ static int config_set(uint32_t key, GVariant *data,
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break;
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}
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}
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if (!strcmp(devc->profile->model, "DSLogic")) {
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if (devc->voltage_threshold == DS_VOLTAGE_RANGE_5_V)
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ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_5V);
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else
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ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_3V3);
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} else if (!strcmp(devc->profile->model, "DSLogic Pro")) {
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ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_PRO_FPGA_FIRMWARE);
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} else if (!strcmp(devc->profile->model, "DSLogic Plus")) {
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ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_PLUS_FPGA_FIRMWARE);
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} else if (!strcmp(devc->profile->model, "DSLogic Basic")) {
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ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_BASIC_FPGA_FIRMWARE);
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}
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ret = dslogic_fpga_firmware_upload(sdi);
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break;
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case SR_CONF_EXTERNAL_CLOCK:
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devc->external_clock = g_variant_get_boolean(data);
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@ -59,12 +59,13 @@ SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
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return SR_OK;
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}
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SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
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const char *name)
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SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi)
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{
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const char *name = NULL;
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uint64_t sum;
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struct sr_resource bitstream;
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struct drv_context *drvc;
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struct dev_context *devc;
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struct sr_usb_dev_inst *usb;
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unsigned char *buf;
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ssize_t chunksize;
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@ -73,8 +74,27 @@ SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
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const uint8_t cmd[3] = {0, 0, 0};
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drvc = sdi->driver->context;
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devc = sdi->priv;
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usb = sdi->conn;
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if (!strcmp(devc->profile->model, "DSLogic")) {
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if (devc->voltage_threshold == DS_VOLTAGE_RANGE_18_33_V)
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name = DSLOGIC_FPGA_FIRMWARE_3V3;
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else
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name = DSLOGIC_FPGA_FIRMWARE_5V;
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} else if (!strcmp(devc->profile->model, "DSLogic Pro")){
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name = DSLOGIC_PRO_FPGA_FIRMWARE;
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} else if (!strcmp(devc->profile->model, "DSLogic Plus")){
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name = DSLOGIC_PLUS_FPGA_FIRMWARE;
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} else if (!strcmp(devc->profile->model, "DSLogic Basic")){
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name = DSLOGIC_BASIC_FPGA_FIRMWARE;
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} else if (!strcmp(devc->profile->model, "DSCope")) {
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name = DSCOPE_FPGA_FIRMWARE;
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} else {
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sr_err("Failed to select FPGA firmware.");
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return SR_ERR;
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}
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sr_dbg("Uploading FPGA firmware '%s'.", name);
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result = sr_resource_open(drvc->sr_ctx, &bitstream,
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@ -148,8 +148,7 @@ struct dslogic_fpga_config {
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#pragma pack(pop)
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SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
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const char *name);
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SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi);
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SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
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SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
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SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
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