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dslogic: Refactored firmware selection into dslogic_fpga_firmware_upload

This commit is contained in:
Joel Holdsworth 2017-06-12 13:19:44 -06:00 committed by Uwe Hermann
parent adcb9951f8
commit 3566348b92
3 changed files with 25 additions and 32 deletions
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30
src/hardware/dslogic/api.c
View File

@ -332,7 +332,6 @@ static int dev_open(struct sr_dev_inst *sdi)
struct sr_dev_driver *di = sdi->driver; struct sr_dev_driver *di = sdi->driver;
struct sr_usb_dev_inst *usb; struct sr_usb_dev_inst *usb;
struct dev_context *devc; struct dev_context *devc;
const char *fpga_firmware = NULL;
int ret; int ret;
int64_t timediff_us, timediff_ms; int64_t timediff_us, timediff_ms;
@ -392,22 +391,8 @@ static int dev_open(struct sr_dev_inst *sdi)
return SR_ERR; return SR_ERR;
} }
if (!strcmp(devc->profile->model, "DSLogic")) {
if (devc->voltage_threshold == DS_VOLTAGE_RANGE_18_33_V)
fpga_firmware = DSLOGIC_FPGA_FIRMWARE_3V3;
else
fpga_firmware = DSLOGIC_FPGA_FIRMWARE_5V;
} else if (!strcmp(devc->profile->model, "DSLogic Pro")){
fpga_firmware = DSLOGIC_PRO_FPGA_FIRMWARE;
} else if (!strcmp(devc->profile->model, "DSLogic Plus")){
fpga_firmware = DSLOGIC_PLUS_FPGA_FIRMWARE;
} else if (!strcmp(devc->profile->model, "DSLogic Basic")){
fpga_firmware = DSLOGIC_BASIC_FPGA_FIRMWARE;
} else if (!strcmp(devc->profile->model, "DSCope")) {
fpga_firmware = DSCOPE_FPGA_FIRMWARE;
}
if ((ret = dslogic_fpga_firmware_upload(sdi, fpga_firmware)) != SR_OK) if ((ret = dslogic_fpga_firmware_upload(sdi)) != SR_OK)
return ret; return ret;
if (devc->cur_samplerate == 0) { if (devc->cur_samplerate == 0) {
@ -574,18 +559,7 @@ static int config_set(uint32_t key, GVariant *data,
break; break;
} }
} }
if (!strcmp(devc->profile->model, "DSLogic")) { ret = dslogic_fpga_firmware_upload(sdi);
if (devc->voltage_threshold == DS_VOLTAGE_RANGE_5_V)
ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_5V);
else
ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_3V3);
} else if (!strcmp(devc->profile->model, "DSLogic Pro")) {
ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_PRO_FPGA_FIRMWARE);
} else if (!strcmp(devc->profile->model, "DSLogic Plus")) {
ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_PLUS_FPGA_FIRMWARE);
} else if (!strcmp(devc->profile->model, "DSLogic Basic")) {
ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_BASIC_FPGA_FIRMWARE);
}
break; break;
case SR_CONF_EXTERNAL_CLOCK: case SR_CONF_EXTERNAL_CLOCK:
devc->external_clock = g_variant_get_boolean(data); devc->external_clock = g_variant_get_boolean(data);

24
src/hardware/dslogic/dslogic.c
View File

@ -59,12 +59,13 @@ SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
return SR_OK; return SR_OK;
} }
SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi, SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi)
const char *name)
{ {
const char *name = NULL;
uint64_t sum; uint64_t sum;
struct sr_resource bitstream; struct sr_resource bitstream;
struct drv_context *drvc; struct drv_context *drvc;
struct dev_context *devc;
struct sr_usb_dev_inst *usb; struct sr_usb_dev_inst *usb;
unsigned char *buf; unsigned char *buf;
ssize_t chunksize; ssize_t chunksize;
@ -73,8 +74,27 @@ SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
const uint8_t cmd[3] = {0, 0, 0}; const uint8_t cmd[3] = {0, 0, 0};
drvc = sdi->driver->context; drvc = sdi->driver->context;
devc = sdi->priv;
usb = sdi->conn; usb = sdi->conn;
if (!strcmp(devc->profile->model, "DSLogic")) {
if (devc->voltage_threshold == DS_VOLTAGE_RANGE_18_33_V)
name = DSLOGIC_FPGA_FIRMWARE_3V3;
else
name = DSLOGIC_FPGA_FIRMWARE_5V;
} else if (!strcmp(devc->profile->model, "DSLogic Pro")){
name = DSLOGIC_PRO_FPGA_FIRMWARE;
} else if (!strcmp(devc->profile->model, "DSLogic Plus")){
name = DSLOGIC_PLUS_FPGA_FIRMWARE;
} else if (!strcmp(devc->profile->model, "DSLogic Basic")){
name = DSLOGIC_BASIC_FPGA_FIRMWARE;
} else if (!strcmp(devc->profile->model, "DSCope")) {
name = DSCOPE_FPGA_FIRMWARE;
} else {
sr_err("Failed to select FPGA firmware.");
return SR_ERR;
}
sr_dbg("Uploading FPGA firmware '%s'.", name); sr_dbg("Uploading FPGA firmware '%s'.", name);
result = sr_resource_open(drvc->sr_ctx, &bitstream, result = sr_resource_open(drvc->sr_ctx, &bitstream,

3
src/hardware/dslogic/dslogic.h
View File

@ -148,8 +148,7 @@ struct dslogic_fpga_config {
#pragma pack(pop) #pragma pack(pop)
SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi, SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi);
const char *name);
SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi); SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi); SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi); SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);