Working trigger on rising and falling edges.
This commit is contained in:
parent
1a7ff3d087
commit
3db03efa4a
|
@ -155,6 +155,100 @@ SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
|
||||||
return SR_OK;
|
return SR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get the session trigger and configure the FPGA structure
|
||||||
|
* accordingly.
|
||||||
|
*/
|
||||||
|
static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
|
||||||
|
struct dslogic_fpga_config *cfg)
|
||||||
|
{
|
||||||
|
struct sr_trigger *trigger;
|
||||||
|
struct sr_trigger_stage *stage;
|
||||||
|
struct sr_trigger_match *match;
|
||||||
|
struct dev_context *devc;
|
||||||
|
const GSList *l, *m;
|
||||||
|
int channelbit, i = 0;
|
||||||
|
uint16_t v16;
|
||||||
|
|
||||||
|
devc = sdi->priv;
|
||||||
|
devc->trigger_en = FALSE;
|
||||||
|
|
||||||
|
cfg->trig_mask0[0] = 0xffff;
|
||||||
|
cfg->trig_mask1[0] = 0xffff;
|
||||||
|
|
||||||
|
cfg->trig_value0[0] = 0;
|
||||||
|
cfg->trig_value1[0] = 0;
|
||||||
|
|
||||||
|
cfg->trig_edge0[0] = 0;
|
||||||
|
cfg->trig_edge1[0] = 0;
|
||||||
|
|
||||||
|
cfg->trig_logic0[0] = 0;
|
||||||
|
cfg->trig_logic1[0] = 0;
|
||||||
|
|
||||||
|
cfg->trig_count0[0] = 0;
|
||||||
|
cfg->trig_count1[0] = 0;
|
||||||
|
|
||||||
|
if (!(trigger = sr_session_trigger_get(sdi->session)))
|
||||||
|
return SR_OK;
|
||||||
|
|
||||||
|
for (l = trigger->stages; l; l = l->next) {
|
||||||
|
stage = l->data;
|
||||||
|
for (m = stage->matches; m; m = m->next) {
|
||||||
|
match = m->data;
|
||||||
|
if (!match->channel->enabled)
|
||||||
|
/* Ignore disabled channels with a trigger. */
|
||||||
|
continue;
|
||||||
|
channelbit = 1 << (match->channel->index);
|
||||||
|
devc->trigger_en = TRUE; /* Triggered. */
|
||||||
|
/* Simple trigger support (event). */
|
||||||
|
if (match->match == SR_TRIGGER_ONE) {
|
||||||
|
cfg->trig_mask0[0] &= ~channelbit;
|
||||||
|
cfg->trig_mask1[0] &= ~channelbit;
|
||||||
|
cfg->trig_value0[0] |= channelbit;
|
||||||
|
cfg->trig_value1[0] |= channelbit;
|
||||||
|
} else if (match->match == SR_TRIGGER_ZERO) {
|
||||||
|
cfg->trig_mask0[0] &= ~channelbit;
|
||||||
|
cfg->trig_mask1[0] &= ~channelbit;
|
||||||
|
} else if (match->match == SR_TRIGGER_FALLING) {
|
||||||
|
cfg->trig_mask0[0] &= ~channelbit;
|
||||||
|
cfg->trig_mask1[0] &= ~channelbit;
|
||||||
|
cfg->trig_edge0[0] |= channelbit;
|
||||||
|
cfg->trig_edge1[0] |= channelbit;
|
||||||
|
} else if (match->match == SR_TRIGGER_RISING) {
|
||||||
|
cfg->trig_mask0[0] &= ~channelbit;
|
||||||
|
cfg->trig_mask1[0] &= ~channelbit;
|
||||||
|
cfg->trig_value0[0] |= channelbit;
|
||||||
|
cfg->trig_value1[0] |= channelbit;
|
||||||
|
cfg->trig_edge0[0] |= channelbit;
|
||||||
|
cfg->trig_edge1[0] |= channelbit;
|
||||||
|
} else if (match->match == SR_TRIGGER_EDGE){
|
||||||
|
cfg->trig_edge0[0] |= channelbit;
|
||||||
|
cfg->trig_edge1[0] |= channelbit;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (devc->trigger_en) {
|
||||||
|
for (i = 1; i < 16; i++) {
|
||||||
|
cfg->trig_mask0[i] = 0xff;
|
||||||
|
cfg->trig_mask1[i] = 0xff;
|
||||||
|
cfg->trig_value0[i] = 0;
|
||||||
|
cfg->trig_value1[i] = 0;
|
||||||
|
cfg->trig_edge0[i] = 0;
|
||||||
|
cfg->trig_edge1[i] = 0;
|
||||||
|
cfg->trig_count0[i] = 0;
|
||||||
|
cfg->trig_count1[i] = 0;
|
||||||
|
cfg->trig_logic0[i] = 2;
|
||||||
|
cfg->trig_logic1[i] = 2;
|
||||||
|
}
|
||||||
|
v16 = RL16(&cfg->mode);
|
||||||
|
v16 |= 1 << 0;
|
||||||
|
WL16(&cfg->mode, v16);
|
||||||
|
}
|
||||||
|
|
||||||
|
return SR_OK;
|
||||||
|
}
|
||||||
|
|
||||||
SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
|
SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
|
||||||
{
|
{
|
||||||
struct dev_context *devc;
|
struct dev_context *devc;
|
||||||
|
@ -207,6 +301,8 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
|
||||||
* 15 1 = internal test mode
|
* 15 1 = internal test mode
|
||||||
* 14 1 = external test mode
|
* 14 1 = external test mode
|
||||||
* 13 1 = loopback test mode
|
* 13 1 = loopback test mode
|
||||||
|
* 12 1 = stream mode
|
||||||
|
* 11 1 = serial trigger
|
||||||
* 8-12 unused
|
* 8-12 unused
|
||||||
* 7 1 = analog mode
|
* 7 1 = analog mode
|
||||||
* 6 1 = samplerate 400MHz
|
* 6 1 = samplerate 400MHz
|
||||||
|
@ -223,14 +319,16 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
|
||||||
v16 = 1 << 14;
|
v16 = 1 << 14;
|
||||||
else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
|
else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
|
||||||
v16 = 1 << 13;
|
v16 = 1 << 13;
|
||||||
if (devc->dslogic_external_clock)
|
//if (devc->dslogic_external_clock)
|
||||||
v16 |= 1 << 2;
|
// v16 |= 1 << 1;
|
||||||
|
//v16 |= 1 << 0;
|
||||||
WL16(&cfg.mode, v16);
|
WL16(&cfg.mode, v16);
|
||||||
|
|
||||||
v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
|
v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
|
||||||
WL32(&cfg.divider, v32);
|
WL32(&cfg.divider, v32);
|
||||||
WL32(&cfg.count, devc->limit_samples);
|
WL32(&cfg.count, devc->limit_samples);
|
||||||
|
|
||||||
|
dslogic_set_trigger(sdi, &cfg);
|
||||||
|
|
||||||
len = sizeof(struct dslogic_fpga_config);
|
len = sizeof(struct dslogic_fpga_config);
|
||||||
ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
|
ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
|
||||||
(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
|
(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
|
||||||
|
|
|
@ -304,6 +304,7 @@ SR_PRIV struct dev_context *fx2lafw_dev_new(void)
|
||||||
devc->limit_samples = 0;
|
devc->limit_samples = 0;
|
||||||
devc->capture_ratio = 0;
|
devc->capture_ratio = 0;
|
||||||
devc->sample_wide = FALSE;
|
devc->sample_wide = FALSE;
|
||||||
|
devc->trigger_en = FALSE;
|
||||||
devc->stl = NULL;
|
devc->stl = NULL;
|
||||||
|
|
||||||
return devc;
|
return devc;
|
||||||
|
@ -440,7 +441,8 @@ SR_PRIV void LIBUSB_CALL fx2lafw_receive_transfer(struct libusb_transfer *transf
|
||||||
} else {
|
} else {
|
||||||
devc->empty_transfer_count = 0;
|
devc->empty_transfer_count = 0;
|
||||||
}
|
}
|
||||||
|
if (devc->trigger_en)
|
||||||
|
devc->trigger_fired = TRUE;
|
||||||
if (devc->trigger_fired) {
|
if (devc->trigger_fired) {
|
||||||
if (!devc->limit_samples || devc->sent_samples < devc->limit_samples) {
|
if (!devc->limit_samples || devc->sent_samples < devc->limit_samples) {
|
||||||
/* Send the incoming transfer to the session bus. */
|
/* Send the incoming transfer to the session bus. */
|
||||||
|
|
|
@ -123,6 +123,7 @@ struct dev_context {
|
||||||
gboolean dslogic;
|
gboolean dslogic;
|
||||||
uint16_t dslogic_mode;
|
uint16_t dslogic_mode;
|
||||||
int dslogic_external_clock;
|
int dslogic_external_clock;
|
||||||
|
gboolean trigger_en;
|
||||||
};
|
};
|
||||||
|
|
||||||
SR_PRIV int fx2lafw_command_start_acquisition(const struct sr_dev_inst *sdi);
|
SR_PRIV int fx2lafw_command_start_acquisition(const struct sr_dev_inst *sdi);
|
||||||
|
|
Loading…
Reference in New Issue