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asix-sigma: use more helpers for bit mask creation 

Rename macros to better reflect which of them check a bit position, and
which span a bit field of given width. Adjust more call sites to use the
macros. This takes tedium out of maintenance as well as review. Has the
minor benefit of somewhat shortening text lines, and eliminating nested
parentheses (or getting perceived as if it would).
This commit is contained in:
Gerhard Sittig 2020-05-17 20:00:21 +02:00
parent 156b6879e9
commit 3f5f548410
3 changed files with 80 additions and 78 deletions
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6
src/hardware/asix-sigma/api.c
View File

@ -477,9 +477,9 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
/* Find which pin to trigger on from mask. */ /* Find which pin to trigger on from mask. */
for (triggerpin = 0; triggerpin < 8; triggerpin++) { for (triggerpin = 0; triggerpin < 8; triggerpin++) {
if (devc->trigger.risingmask & (1 << triggerpin)) if (devc->trigger.risingmask & BIT(triggerpin))
break; break;
if (devc->trigger.fallingmask & (1 << triggerpin)) if (devc->trigger.fallingmask & BIT(triggerpin))
break; break;
} }
@ -550,7 +550,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
* Derive a mask where bits are set for unavailable channels. * Derive a mask where bits are set for unavailable channels.
* Either send the single byte, or the full byte sequence. * Either send the single byte, or the full byte sequence.
*/ */
pindis_mask = ~((1UL << devc->num_channels) - 1); pindis_mask = ~BITS_MASK(devc->num_channels);
if (devc->clock.samplerate > SR_MHZ(50)) { if (devc->clock.samplerate > SR_MHZ(50)) {
ret = sigma_set_register(devc, WRITE_CLOCK_SELECT, ret = sigma_set_register(devc, WRITE_CLOCK_SELECT,
pindis_mask & 0xff); pindis_mask & 0xff);

60
src/hardware/asix-sigma/protocol.c
View File

@ -446,49 +446,49 @@ SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc,
* which combines pin levels or edges. * which combines pin levels or edges.
*/ */
for (lut_addr = 0; lut_addr < 16; lut_addr++) { for (lut_addr = 0; lut_addr < 16; lut_addr++) {
bit = 1 << lut_addr; bit = BIT(lut_addr);
/* - M4 M3S M3Q */ /* - M4 M3S M3Q */
m3d = 0; m3d = 0;
if (lut->m4 & bit) if (lut->m4 & bit)
m3d |= 1 << 2; m3d |= BIT(2);
if (lut->m3s & bit) if (lut->m3s & bit)
m3d |= 1 << 1; m3d |= BIT(1);
if (lut->m3q & bit) if (lut->m3q & bit)
m3d |= 1 << 0; m3d |= BIT(0);
/* M2D3 M2D2 M2D1 M2D0 */ /* M2D3 M2D2 M2D1 M2D0 */
m2d = 0; m2d = 0;
if (lut->m2d[3] & bit) if (lut->m2d[3] & bit)
m2d |= 1 << 3; m2d |= BIT(3);
if (lut->m2d[2] & bit) if (lut->m2d[2] & bit)
m2d |= 1 << 2; m2d |= BIT(2);
if (lut->m2d[1] & bit) if (lut->m2d[1] & bit)
m2d |= 1 << 1; m2d |= BIT(1);
if (lut->m2d[0] & bit) if (lut->m2d[0] & bit)
m2d |= 1 << 0; m2d |= BIT(0);
/* M1D3 M1D2 M1D1 M1D0 */ /* M1D3 M1D2 M1D1 M1D0 */
m1d = 0; m1d = 0;
if (lut->m1d[3] & bit) if (lut->m1d[3] & bit)
m1d |= 1 << 3; m1d |= BIT(3);
if (lut->m1d[2] & bit) if (lut->m1d[2] & bit)
m1d |= 1 << 2; m1d |= BIT(2);
if (lut->m1d[1] & bit) if (lut->m1d[1] & bit)
m1d |= 1 << 1; m1d |= BIT(1);
if (lut->m1d[0] & bit) if (lut->m1d[0] & bit)
m1d |= 1 << 0; m1d |= BIT(0);
/* M0D3 M0D2 M0D1 M0D0 */ /* M0D3 M0D2 M0D1 M0D0 */
m0d = 0; m0d = 0;
if (lut->m0d[3] & bit) if (lut->m0d[3] & bit)
m0d |= 1 << 3; m0d |= BIT(3);
if (lut->m0d[2] & bit) if (lut->m0d[2] & bit)
m0d |= 1 << 2; m0d |= BIT(2);
if (lut->m0d[1] & bit) if (lut->m0d[1] & bit)
m0d |= 1 << 1; m0d |= BIT(1);
if (lut->m0d[0] & bit) if (lut->m0d[0] & bit)
m0d |= 1 << 0; m0d |= BIT(0);
/* /*
* Send 16bits with M3D/M2D and M1D/M0D bit masks to the * Send 16bits with M3D/M2D and M1D/M0D bit masks to the
@ -553,14 +553,14 @@ SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc,
* mode and sending configuration data. Set D7 and toggle D2, D3, D4 * mode and sending configuration data. Set D7 and toggle D2, D3, D4
* a few times. * a few times.
*/ */
#define BB_PIN_CCLK (1 << 0) /* D0, CCLK */ #define BB_PIN_CCLK BIT(0) /* D0, CCLK */
#define BB_PIN_PROG (1 << 1) /* D1, PROG */ #define BB_PIN_PROG BIT(1) /* D1, PROG */
#define BB_PIN_D2 (1 << 2) /* D2, (part of) SUICIDE */ #define BB_PIN_D2 BIT(2) /* D2, (part of) SUICIDE */
#define BB_PIN_D3 (1 << 3) /* D3, (part of) SUICIDE */ #define BB_PIN_D3 BIT(3) /* D3, (part of) SUICIDE */
#define BB_PIN_D4 (1 << 4) /* D4, (part of) SUICIDE (unused?) */ #define BB_PIN_D4 BIT(4) /* D4, (part of) SUICIDE (unused?) */
#define BB_PIN_INIT (1 << 5) /* D5, INIT, input pin */ #define BB_PIN_INIT BIT(5) /* D5, INIT, input pin */
#define BB_PIN_DIN (1 << 6) /* D6, DIN */ #define BB_PIN_DIN BIT(6) /* D6, DIN */
#define BB_PIN_D7 (1 << 7) /* D7, (part of) SUICIDE */ #define BB_PIN_D7 BIT(7) /* D7, (part of) SUICIDE */
#define BB_BITRATE (750 * 1000) #define BB_BITRATE (750 * 1000)
#define BB_PINMASK (0xff & ~BB_PIN_INIT) #define BB_PINMASK (0xff & ~BB_PIN_INIT)
@ -1312,7 +1312,7 @@ SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi)
/* Ignore disabled channels with a trigger. */ /* Ignore disabled channels with a trigger. */
if (!match->channel->enabled) if (!match->channel->enabled)
continue; continue;
channelbit = 1 << match->channel->index; channelbit = BIT(match->channel->index);
if (devc->clock.samplerate >= SR_MHZ(100)) { if (devc->clock.samplerate >= SR_MHZ(100)) {
/* Fast trigger support. */ /* Fast trigger support. */
if (trigger_set) { if (trigger_set) {
@ -1813,7 +1813,7 @@ static void build_lut_entry(uint16_t *lut_entry,
lut_entry[quad] = ~0; lut_entry[quad] = ~0;
for (bitidx = 0; bitidx < 16; bitidx++) { for (bitidx = 0; bitidx < 16; bitidx++) {
for (ch = 0; ch < 4; ch++) { for (ch = 0; ch < 4; ch++) {
quadmask = 1 << ch; quadmask = BIT(ch);
bitmask = quadmask << (quad * 4); bitmask = quadmask << (quad * 4);
if (!(spec_mask & bitmask)) if (!(spec_mask & bitmask))
continue; continue;
@ -1829,7 +1829,7 @@ static void build_lut_entry(uint16_t *lut_entry,
bit_idx_low = !(bitidx & quadmask); bit_idx_low = !(bitidx & quadmask);
if (spec_value_low == bit_idx_low) if (spec_value_low == bit_idx_low)
continue; continue;
lut_entry[quad] &= ~(1 << bitidx); lut_entry[quad] &= ~BIT(bitidx);
} }
} }
} }
@ -1910,10 +1910,10 @@ static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
rset = !rset; rset = !rset;
*mask &= ~(1 << i); *mask &= ~BIT(i);
if (rset) if (rset)
*mask |= 1 << i; *mask |= BIT(i);
} }
} }
@ -1947,7 +1947,7 @@ SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc,
memset(&masks, 0, sizeof(masks)); memset(&masks, 0, sizeof(masks));
condidx = 0; condidx = 0;
for (bitidx = 0; bitidx < 16; bitidx++) { for (bitidx = 0; bitidx < 16; bitidx++) {
mask = 1 << bitidx; mask = BIT(bitidx);
value = devc->trigger.risingmask | devc->trigger.fallingmask; value = devc->trigger.risingmask | devc->trigger.fallingmask;
if (!(value & mask)) if (!(value & mask))
continue; continue;

92
src/hardware/asix-sigma/protocol.h
View File

@ -54,6 +54,13 @@ enum asix_device_type {
ASIX_TYPE_OMEGA, ASIX_TYPE_OMEGA,
}; };
/* Mask to isolate one bit, mask to span a number of bits. */
#define BIT(pos) (1UL << (pos))
#define BITS_MASK(count) ((1UL << (count)) - 1)
#define HI4(b) (((b) >> 4) & 0x0f)
#define LO4(b) (((b) >> 0) & 0x0f)
/* /*
* FPGA commands are 8bits wide. The upper nibble is a command opcode, * FPGA commands are 8bits wide. The upper nibble is a command opcode,
* the lower nibble can carry operand values. 8bit register addresses * the lower nibble can carry operand values. 8bit register addresses
@ -66,8 +73,8 @@ enum asix_device_type {
#define REG_DATA_LOW (0x2 << 4) #define REG_DATA_LOW (0x2 << 4)
#define REG_DATA_HIGH_WRITE (0x3 << 4) #define REG_DATA_HIGH_WRITE (0x3 << 4)
#define REG_READ_ADDR (0x4 << 4) #define REG_READ_ADDR (0x4 << 4)
#define REG_ADDR_ADJUST (1 << 0) /* Auto adjust register address. */ #define REG_ADDR_ADJUST BIT(0) /* Auto adjust register address. */
#define REG_ADDR_DOWN (1 << 1) /* 1 decrement, 0 increment. */ #define REG_ADDR_DOWN BIT(1) /* 1 decrement, 0 increment. */
#define REG_ADDR_INC (REG_ADDR_ADJUST) #define REG_ADDR_INC (REG_ADDR_ADJUST)
#define REG_ADDR_DEC (REG_ADDR_ADJUST | REG_ADDR_DOWN) #define REG_ADDR_DEC (REG_ADDR_ADJUST | REG_ADDR_DOWN)
@ -134,27 +141,22 @@ enum sigma_read_register {
/* Reserved for plugin features. See above. */ /* Reserved for plugin features. See above. */
}; };
#define HI4(b) (((b) >> 4) & 0x0f) #define CLKSEL_CLKSEL8 BIT(0)
#define LO4(b) (((b) >> 0) & 0x0f) #define CLKSEL_PINMASK BITS_MASK(4)
#define CLKSEL_RISING BIT(4)
#define CLKSEL_FALLING BIT(5)
#define BIT_MASK(l) ((1UL << (l)) - 1) #define TRGSEL_SELINC_MASK BITS_MASK(2)
#define CLKSEL_CLKSEL8 (1 << 0)
#define CLKSEL_PINMASK BIT_MASK(4)
#define CLKSEL_RISING (1 << 4)
#define CLKSEL_FALLING (1 << 5)
#define TRGSEL_SELINC_MASK BIT_MASK(2)
#define TRGSEL_SELINC_SHIFT 0 #define TRGSEL_SELINC_SHIFT 0
#define TRGSEL_SELRES_MASK BIT_MASK(2) #define TRGSEL_SELRES_MASK BITS_MASK(2)
#define TRGSEL_SELRES_SHIFT 2 #define TRGSEL_SELRES_SHIFT 2
#define TRGSEL_SELA_MASK BIT_MASK(2) #define TRGSEL_SELA_MASK BITS_MASK(2)
#define TRGSEL_SELA_SHIFT 4 #define TRGSEL_SELA_SHIFT 4
#define TRGSEL_SELB_MASK BIT_MASK(2) #define TRGSEL_SELB_MASK BITS_MASK(2)
#define TRGSEL_SELB_SHIFT 6 #define TRGSEL_SELB_SHIFT 6
#define TRGSEL_SELC_MASK BIT_MASK(2) #define TRGSEL_SELC_MASK BITS_MASK(2)
#define TRGSEL_SELC_SHIFT 8 #define TRGSEL_SELC_SHIFT 8
#define TRGSEL_SELPRESC_MASK BIT_MASK(4) #define TRGSEL_SELPRESC_MASK BITS_MASK(4)
#define TRGSEL_SELPRESC_SHIFT 12 #define TRGSEL_SELPRESC_SHIFT 12
enum trgsel_selcode_t { enum trgsel_selcode_t {
@ -165,48 +167,48 @@ enum trgsel_selcode_t {
TRGSEL_SELCODE_NEVER = 3, TRGSEL_SELCODE_NEVER = 3,
}; };
#define TRGSEL2_PINS_MASK BIT_MASK(3) #define TRGSEL2_PINS_MASK BITS_MASK(3)
#define TRGSEL2_PINPOL_RISE (1 << 3) #define TRGSEL2_PINPOL_RISE BIT(3)
#define TRGSEL2_LUT_ADDR_MASK BIT_MASK(4) #define TRGSEL2_LUT_ADDR_MASK BITS_MASK(4)
#define TRGSEL2_LUT_WRITE (1 << 4) #define TRGSEL2_LUT_WRITE BIT(4)
#define TRGSEL2_RESET (1 << 5) #define TRGSEL2_RESET BIT(5)
#define TRGSEL2_LEDSEL0 (1 << 6) #define TRGSEL2_LEDSEL0 BIT(6)
#define TRGSEL2_LEDSEL1 (1 << 7) #define TRGSEL2_LEDSEL1 BIT(7)
/* WRITE_MODE register fields. */ /* WRITE_MODE register fields. */
#define WMR_SDRAMWRITEEN (1 << 0) #define WMR_SDRAMWRITEEN BIT(0)
#define WMR_SDRAMREADEN (1 << 1) #define WMR_SDRAMREADEN BIT(1)
#define WMR_TRGRES (1 << 2) #define WMR_TRGRES BIT(2)
#define WMR_TRGEN (1 << 3) #define WMR_TRGEN BIT(3)
#define WMR_FORCESTOP (1 << 4) #define WMR_FORCESTOP BIT(4)
#define WMR_TRGSW (1 << 5) #define WMR_TRGSW BIT(5)
/* not used: bit position 6 */ /* not used: bit position 6 */
#define WMR_SDRAMINIT (1 << 7) #define WMR_SDRAMINIT BIT(7)
/* READ_MODE register fields. */ /* READ_MODE register fields. */
#define RMR_SDRAMWRITEEN (1 << 0) #define RMR_SDRAMWRITEEN BIT(0)
#define RMR_SDRAMREADEN (1 << 1) #define RMR_SDRAMREADEN BIT(1)
/* not used: bit position 2 */ /* not used: bit position 2 */
#define RMR_TRGEN (1 << 3) #define RMR_TRGEN BIT(3)
#define RMR_ROUND (1 << 4) #define RMR_ROUND BIT(4)
#define RMR_TRIGGERED (1 << 5) #define RMR_TRIGGERED BIT(5)
#define RMR_POSTTRIGGERED (1 << 6) #define RMR_POSTTRIGGERED BIT(6)
/* not used: bit position 7 */ /* not used: bit position 7 */
/* /*
* Trigger options. First and second write are similar, but _some_ * Trigger options. First and second write are similar, but _some_
* positions change their meaning. * positions change their meaning.
*/ */
#define TRGOPT_TRGIEN (1 << 7) #define TRGOPT_TRGIEN BIT(7)
#define TRGOPT_TRGOEN (1 << 6) #define TRGOPT_TRGOEN BIT(6)
#define TRGOPT_TRGOINEN (1 << 5) /* 1st write */ #define TRGOPT_TRGOINEN BIT(5) /* 1st write */
#define TRGOPT_TRGINEG TRGOPT1_TRGOINEN /* 2nd write */ #define TRGOPT_TRGINEG TRGOPT1_TRGOINEN /* 2nd write */
#define TRGOPT_TRGOEVNTEN (1 << 4) /* 1st write */ #define TRGOPT_TRGOEVNTEN BIT(4) /* 1st write */
#define TRGOPT_TRGOPIN TRGOPT1_TRGOEVNTEN /* 2nd write */ #define TRGOPT_TRGOPIN TRGOPT1_TRGOEVNTEN /* 2nd write */
#define TRGOPT_TRGOOUTEN (1 << 3) /* 1st write */ #define TRGOPT_TRGOOUTEN BIT(3) /* 1st write */
#define TRGOPT_TRGOLONG TRGOPT1_TRGOOUTEN /* 2nd write */ #define TRGOPT_TRGOLONG TRGOPT1_TRGOOUTEN /* 2nd write */
#define TRGOPT_TRGOUTR_OUT (1 << 1) #define TRGOPT_TRGOUTR_OUT BIT(1)
#define TRGOPT_TRGOUTR_EN (1 << 0) #define TRGOPT_TRGOUTR_EN BIT(0)
#define TRGOPT_CLEAR_MASK (TRGOPT_TRGOINEN | TRGOPT_TRGOEVNTEN | TRGOPT_TRGOOUTEN) #define TRGOPT_CLEAR_MASK (TRGOPT_TRGOINEN | TRGOPT_TRGOEVNTEN | TRGOPT_TRGOOUTEN)
/* /*
@ -245,7 +247,7 @@ enum trgsel_selcode_t {
#define ROW_LENGTH_BYTES 1024 #define ROW_LENGTH_BYTES 1024
#define ROW_LENGTH_U16 (ROW_LENGTH_BYTES / sizeof(uint16_t)) #define ROW_LENGTH_U16 (ROW_LENGTH_BYTES / sizeof(uint16_t))
#define ROW_SHIFT 9 /* log2 of u16 count */ #define ROW_SHIFT 9 /* log2 of u16 count */
#define ROW_MASK ((1UL << ROW_SHIFT) - 1) #define ROW_MASK BITS_MASK(ROW_SHIFT)
#define EVENTS_PER_CLUSTER 7 #define EVENTS_PER_CLUSTER 7
#define CLUSTERS_PER_ROW (ROW_LENGTH_U16 / (1 + EVENTS_PER_CLUSTER)) #define CLUSTERS_PER_ROW (ROW_LENGTH_U16 / (1 + EVENTS_PER_CLUSTER))
#define EVENTS_PER_ROW (CLUSTERS_PER_ROW * EVENTS_PER_CLUSTER) #define EVENTS_PER_ROW (CLUSTERS_PER_ROW * EVENTS_PER_CLUSTER)