rigol-ds: Fix memory buffer readout on DS4000 series.
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@ -208,7 +208,7 @@ static const struct rigol_ds_series supported_series[] = {
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[DS1000Z] = {VENDOR(RIGOL), "DS1000Z", PROTOCOL_V4, FORMAT_IEEE488_2,
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[DS1000Z] = {VENDOR(RIGOL), "DS1000Z", PROTOCOL_V4, FORMAT_IEEE488_2,
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{50, 1}, {1, 1000}, 12, 1200, 12000000},
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{50, 1}, {1, 1000}, 12, 1200, 12000000},
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[DS4000] = {VENDOR(RIGOL), "DS4000", PROTOCOL_V4, FORMAT_IEEE488_2,
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[DS4000] = {VENDOR(RIGOL), "DS4000", PROTOCOL_V4, FORMAT_IEEE488_2,
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{1000, 1}, {1, 1000}, 14, 1400, 14000},
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{1000, 1}, {1, 1000}, 14, 1400, 0},
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[MSO7000A] = {VENDOR(AGILENT), "MSO7000A", PROTOCOL_V4, FORMAT_IEEE488_2,
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[MSO7000A] = {VENDOR(AGILENT), "MSO7000A", PROTOCOL_V4, FORMAT_IEEE488_2,
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{50, 1}, {2, 1000}, 10, 1000, 8000000},
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{50, 1}, {2, 1000}, 10, 1000, 8000000},
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};
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};
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@ -333,6 +333,7 @@ SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi)
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struct dev_context *devc;
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struct dev_context *devc;
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gchar *trig_mode;
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gchar *trig_mode;
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unsigned int num_channels, i, j;
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unsigned int num_channels, i, j;
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int buffer_samples;
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if (!(devc = sdi->priv))
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if (!(devc = sdi->priv))
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return SR_ERR;
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return SR_ERR;
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@ -398,12 +399,29 @@ SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi)
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}
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}
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}
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}
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buffer_samples = devc->model->series->buffer_samples;
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if (buffer_samples == 0)
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{
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/* The DS4000 series does not have a fixed memory depth, it
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* can be chosen from the menu and also varies with number
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* of active channels. Retrieve the actual number with the
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* ACQ:MDEP command. */
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sr_scpi_get_int(sdi->conn, "ACQ:MDEP?", &buffer_samples);
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devc->analog_frame_size = devc->digital_frame_size =
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buffer_samples;
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}
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else
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{
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/* The DS1000Z series has a fixed memory depth which we
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* need to divide correctly according to the number of
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* active channels. */
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devc->analog_frame_size = devc->digital_frame_size =
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devc->analog_frame_size = devc->digital_frame_size =
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num_channels == 1 ?
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num_channels == 1 ?
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devc->model->series->buffer_samples :
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buffer_samples :
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num_channels == 2 ?
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num_channels == 2 ?
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devc->model->series->buffer_samples / 2 :
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buffer_samples / 2 :
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devc->model->series->buffer_samples / 4;
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buffer_samples / 4;
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}
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}
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}
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if (rigol_ds_config_set(sdi, ":SING") != SR_OK)
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if (rigol_ds_config_set(sdi, ":SING") != SR_OK)
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