rigol-ds1xx2: Fix setting trigger parameters.
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parent
542843f76f
commit
4e108ace13
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@ -295,7 +295,7 @@ static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
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break;
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case SR_HWCAP_TRIGGER_SLOPE:
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tmp_u64 = *(const int *)value;
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rigol_ds1xx2_send_data(devc->fd, ":TRIG:EDGE:%s\n", tmp_u64 ? "POS" : "NEG");
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rigol_ds1xx2_send_data(devc->fd, ":TRIG:EDGE:SLOP %s\n", tmp_u64 ? "POS" : "NEG");
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break;
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case SR_HWCAP_HORIZ_TRIGGERPOS:
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tmp_float = *(const float *)value;
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@ -315,9 +315,11 @@ static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
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else if (!strcmp(value, "AC Line"))
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channel = "ACL";
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else
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{
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ret = SR_ERR_ARG;
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break;
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rigol_ds1xx2_send_data(devc->fd, ":TRIG:SOUR %s\n", channel);
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}
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rigol_ds1xx2_send_data(devc->fd, ":TRIG:EDGE:SOUR %s\n", channel);
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break;
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case SR_HWCAP_VDIV:
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/* TODO: Not supporting vdiv per channel yet. */
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