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sysclk-lwla: Clarify use of SRAM control registers 

Assign more meaningful names to things and introduce new constants.
This commit is contained in:
Daniel Elstner 2015-10-31 01:11:31 +01:00
parent a6dc3dacab
commit 586ff70a21
2 changed files with 18 additions and 11 deletions
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13
src/hardware/sysclk-lwla/lwla.h
View File

@ -74,12 +74,12 @@ enum {
STATUS_FLAG_MASK = 0x3F STATUS_FLAG_MASK = 0x3F
}; };
/** LWLA register addresses. /** LWLA1034 register addresses.
*/ */
enum { enum {
REG_MEM_CTRL2 = 0x1074, /* capture buffer control ??? */ REG_MEM_CTRL = 0x1074, /* capture buffer control */
REG_MEM_FILL = 0x1078, /* capture buffer fill level */ REG_MEM_FILL = 0x1078, /* capture buffer fill level */
REG_MEM_CTRL4 = 0x107C, /* capture buffer control ??? */ REG_MEM_START = 0x107C, /* capture buffer start address */
REG_DIV_BYPASS = 0x1094, /* bypass clock divider flag */ REG_DIV_BYPASS = 0x1094, /* bypass clock divider flag */
@ -94,6 +94,13 @@ enum {
REG_FREQ_CH4 = 0x10CC, /* channel 4 live frequency */ REG_FREQ_CH4 = 0x10CC, /* channel 4 live frequency */
}; };
/** Flag bits for REG_MEM_CTRL.
*/
enum {
MEM_CTRL_WRITE = 1 << 0, /* "wr1rd0" bit */
MEM_CTRL_CLR_IDX = 1 << 1, /* "clr_idx" bit */
};
/** Register/value pair. /** Register/value pair.
*/ */
struct regval_pair { struct regval_pair {

16
src/hardware/sysclk-lwla/protocol.c
View File

@ -257,10 +257,10 @@ static void issue_read_start(const struct sr_dev_inst *sdi)
regvals[0].reg = REG_DIV_BYPASS; regvals[0].reg = REG_DIV_BYPASS;
regvals[0].val = 1; regvals[0].val = 1;
regvals[1].reg = REG_MEM_CTRL2; regvals[1].reg = REG_MEM_CTRL;
regvals[1].val = 2; regvals[1].val = MEM_CTRL_CLR_IDX;
regvals[2].reg = REG_MEM_CTRL4; regvals[2].reg = REG_MEM_START;
regvals[2].val = 4; regvals[2].val = 4;
devc->reg_write_pos = 0; devc->reg_write_pos = 0;
@ -723,7 +723,7 @@ SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi)
return ret; return ret;
if (value != UINT64_C(0x1234567887654321)) { if (value != UINT64_C(0x1234567887654321)) {
sr_err("Received invalid test word 0x%16" PRIX64 ".", value); sr_err("Received invalid test word 0x%016" PRIX64 ".", value);
return SR_ERR; return SR_ERR;
} }
return SR_OK; return SR_OK;
@ -814,11 +814,11 @@ SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi)
sr_info("External clock, rising edge."); sr_info("External clock, rising edge.");
} }
regvals[0].reg = REG_MEM_CTRL2; regvals[0].reg = REG_MEM_CTRL;
regvals[0].val = 2; regvals[0].val = MEM_CTRL_CLR_IDX;
regvals[1].reg = REG_MEM_CTRL2; regvals[1].reg = REG_MEM_CTRL;
regvals[1].val = 1; regvals[1].val = MEM_CTRL_WRITE;
regvals[2].reg = REG_LONG_ADDR; regvals[2].reg = REG_LONG_ADDR;
regvals[2].val = 10; regvals[2].val = 10;