saleae-logic16: Clearer error message.

This commit is contained in:
Bert Vermeulen 2014-11-27 01:00:40 +01:00
parent e743a47d6d
commit 5cfcab6603
1 changed files with 3 additions and 3 deletions

View File

@ -470,7 +470,7 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
reg1 &= ~0x20; reg1 &= ~0x20;
if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x08) { if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x08) {
sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08.", reg1); sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x08.", reg1);
return SR_ERR; return SR_ERR;
} }
@ -499,7 +499,7 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
return ret; return ret;
if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) { if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) {
sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48. " sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x48. "
"Proceeding anyway.", reg1); "Proceeding anyway.", reg1);
} }
@ -507,7 +507,7 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
return ret; return ret;
if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg10 != clock_select) { if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg10 != clock_select) {
sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x%02x.", sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x.",
reg10, clock_select); reg10, clock_select);
return SR_ERR; return SR_ERR;
} }