sysclk-lwla: Work around short transfer quirk
Detect whether the FX2 firmware of the LWLA device exhibits the short transfer bug. If so, work around the problem by limiting reads to at most 64 bytes at a time. This slows down the memory read after acquisition quite noticably, but makes the device usable even in adverse conditions.
This commit is contained in:
Daniel Elstner
parent
940805ce7d
commit
786485772f
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@ -329,10 +329,13 @@ static int dev_open(struct sr_dev_inst *sdi)
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sr_usb_close(usb);
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return ret;
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}
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/* This delay appears to be necessary for reliable operation. */
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g_usleep(30 * 1000);
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sdi->status = SR_ST_ACTIVE;
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devc->active_fpga_config = FPGA_NOCONF;
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devc->short_transfer_quirk = FALSE;
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devc->state = STATE_IDLE;
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ret = (*devc->model->apply_fpga_config)(sdi);
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@ -343,8 +346,12 @@ static int dev_open(struct sr_dev_inst *sdi)
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if (ret != SR_OK) {
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sdi->status = SR_ST_INACTIVE;
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sr_usb_close(usb);
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return ret;
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}
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return ret;
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if (devc->short_transfer_quirk)
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sr_warn("Short transfer quirk detected! "
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"Memory reads will be slow.");
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return SR_OK;
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}
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/* Shutdown and close device.
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@ -144,33 +144,26 @@ SR_PRIV int lwla_send_command(const struct sr_usb_dev_inst *usb,
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}
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SR_PRIV int lwla_receive_reply(const struct sr_usb_dev_inst *usb,
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uint32_t *reply, int reply_len, int expect_len)
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void *reply, int buf_size, int *xfer_len)
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{
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int ret;
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int xfer_len;
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if (!usb || !reply || reply_len <= 0)
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if (!usb || !reply || buf_size <= 0)
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return SR_ERR_BUG;
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xfer_len = 0;
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ret = libusb_bulk_transfer(usb->devhdl, EP_REPLY,
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(unsigned char *)reply, reply_len * 4,
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&xfer_len, USB_TIMEOUT_MS);
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ret = libusb_bulk_transfer(usb->devhdl, EP_REPLY, reply, buf_size,
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xfer_len, USB_TIMEOUT_MS);
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if (ret != 0) {
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sr_dbg("Failed to receive reply: %s.", libusb_error_name(ret));
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return SR_ERR;
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}
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if (xfer_len != expect_len * 4) {
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sr_dbg("Failed to receive reply: incorrect length %d != %d.",
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xfer_len, expect_len * 4);
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return SR_ERR;
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}
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return SR_OK;
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}
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SR_PRIV int lwla_read_reg(const struct sr_usb_dev_inst *usb,
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uint16_t reg, uint32_t *value)
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{
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int xfer_len;
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int ret;
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uint16_t command[2];
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uint32_t reply[128]; /* full EP buffer to avoid overflows */
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@ -179,16 +172,21 @@ SR_PRIV int lwla_read_reg(const struct sr_usb_dev_inst *usb,
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command[1] = LWLA_WORD(reg);
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ret = lwla_send_command(usb, command, ARRAY_SIZE(command));
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if (ret != SR_OK)
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return ret;
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ret = lwla_receive_reply(usb, reply, ARRAY_SIZE(reply), 1);
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ret = lwla_receive_reply(usb, reply, sizeof(reply), &xfer_len);
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if (ret != SR_OK)
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return ret;
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if (ret == SR_OK)
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*value = LWLA_TO_UINT32(reply[0]);
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if (xfer_len != 4) {
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sr_dbg("Invalid register read response of length %d.",
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xfer_len);
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return SR_ERR;
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}
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*value = LWLA_TO_UINT32(reply[0]);
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return ret;
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return SR_OK;
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}
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SR_PRIV int lwla_write_reg(const struct sr_usb_dev_inst *usb,
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@ -154,7 +154,7 @@ SR_PRIV int lwla_send_command(const struct sr_usb_dev_inst *usb,
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const uint16_t *command, int cmd_len);
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SR_PRIV int lwla_receive_reply(const struct sr_usb_dev_inst *usb,
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uint32_t *reply, int reply_len, int expect_len);
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void *reply, int buf_size, int *xfer_len);
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SR_PRIV int lwla_read_reg(const struct sr_usb_dev_inst *usb,
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uint16_t reg, uint32_t *value);
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@ -35,11 +35,11 @@
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/* Capture memory read start address.
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*/
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#define READ_START_ADDR 2
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#define READ_START_ADDR 2
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/* Number of device memory units (32 bit) to read at a time.
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*/
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#define READ_CHUNK_LEN32 250
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#define READ_CHUNK_LEN 250
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/** LWLA1016 register addresses.
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*/
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@ -182,6 +182,58 @@ static void read_response_rle(struct acquisition_state *acq)
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acq->mem_addr_done += wi;
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}
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/* Check whether we can receive responses of more than 64 bytes.
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* The FX2 firmware of the LWLA1016 has a bug in the reset logic which
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* sometimes causes the response endpoint to be limited to transfers of
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* 64 bytes at a time, instead of the expected 2*512 bytes. The problem
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* can be worked around by never requesting more than 64 bytes.
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* This quirk manifests itself only under certain conditions, and some
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* users seem to see it more frequently than others. Detect it here in
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* order to avoid paying the penalty unnecessarily.
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*/
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static int test_read_memory(const struct sr_dev_inst *sdi,
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unsigned int start, unsigned int count)
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{
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struct dev_context *devc;
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struct sr_usb_dev_inst *usb;
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unsigned int i;
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int xfer_len;
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int ret;
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uint16_t command[5];
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unsigned char reply[512];
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devc = sdi->priv;
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usb = sdi->conn;
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command[0] = LWLA_WORD(CMD_READ_MEM32);
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command[1] = LWLA_WORD_0(start);
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command[2] = LWLA_WORD_1(start);
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command[3] = LWLA_WORD_0(count);
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command[4] = LWLA_WORD_1(count);
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ret = lwla_send_command(usb, command, ARRAY_SIZE(command));
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if (ret != SR_OK)
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return ret;
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ret = lwla_receive_reply(usb, reply, sizeof(reply), &xfer_len);
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if (ret != SR_OK)
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return ret;
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devc->short_transfer_quirk = (xfer_len == 64);
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for (i = xfer_len; i < 4 * count && xfer_len == 64; i += xfer_len) {
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ret = lwla_receive_reply(usb, reply, sizeof(reply), &xfer_len);
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if (ret != SR_OK)
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return ret;
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}
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if (i != 4 * count) {
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sr_err("Invalid read response of unexpected length %d.",
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xfer_len);
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return SR_ERR;
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}
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return SR_OK;
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}
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/* Select and transfer FPGA bitstream for the current configuration.
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*/
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static int apply_fpga_config(const struct sr_dev_inst *sdi)
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@ -213,9 +265,15 @@ static int apply_fpga_config(const struct sr_dev_inst *sdi)
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*/
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static int device_init_check(const struct sr_dev_inst *sdi)
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{
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static const struct regval mem_reset[] = {
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{REG_MEM_CTRL, MEM_CTRL_RESET},
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{REG_MEM_CTRL, 0},
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};
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uint32_t value;
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int ret;
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const unsigned int test_count = 24;
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ret = lwla_read_reg(sdi->conn, REG_TEST_ID, &value);
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if (ret != SR_OK)
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return ret;
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@ -229,7 +287,19 @@ static int device_init_check(const struct sr_dev_inst *sdi)
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sr_err("Received invalid test word 0x%08X.", value);
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return SR_ERR;
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}
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return SR_OK;
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ret = lwla_write_regs(sdi->conn, mem_reset, ARRAY_SIZE(mem_reset));
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if (ret != SR_OK)
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return ret;
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ret = test_read_memory(sdi, 0, test_count);
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if (ret != SR_OK)
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return ret;
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/*
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* Issue another read request or the device will stall, for whatever
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* reason. This happens both with and without the short transfer quirk.
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*/
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return test_read_memory(sdi, test_count, test_count);
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}
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static int setup_acquisition(const struct sr_dev_inst *sdi)
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@ -285,7 +355,7 @@ static int prepare_request(const struct sr_dev_inst *sdi)
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{
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struct dev_context *devc;
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struct acquisition_state *acq;
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unsigned int count;
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unsigned int chunk_len, count;
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devc = sdi->priv;
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acq = devc->acquisition;
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@ -319,8 +389,10 @@ static int prepare_request(const struct sr_dev_inst *sdi)
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lwla_queue_regval(acq, REG_CAP_COUNT, 0);
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break;
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case STATE_READ_REQUEST:
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count = MIN(READ_CHUNK_LEN32,
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acq->mem_addr_stop - acq->mem_addr_next);
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/* Limit reads to 16 device words (64 bytes) at a time if the
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* device firmware has the short transfer quirk. */
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chunk_len = (devc->short_transfer_quirk) ? 16 : READ_CHUNK_LEN;
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count = MIN(chunk_len, acq->mem_addr_stop - acq->mem_addr_next);
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acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM32);
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acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
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@ -39,7 +39,7 @@
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/* Capture memory read start address.
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*/
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#define READ_START_ADDR 4
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#define READ_START_ADDR 4
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/* Number of device memory units (36 bit) to read at a time. Slices of 8
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* consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk
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@ -54,7 +54,7 @@
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* a time. So far, it appears safe to increase this to 224 words (28 slices,
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* 1008 bytes), thus making the most of two 512 byte buffers.
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*/
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#define READ_CHUNK_LEN36 (28 * 8)
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#define READ_CHUNK_LEN (28 * 8)
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/* Bit mask for the RLE repeat-count-follows flag.
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*/
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@ -266,6 +266,60 @@ static void read_response(struct acquisition_state *acq)
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acq->mem_addr_done += wi;
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}
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/* Check whether we can receive responses of more than 64 bytes.
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* The FX2 firmware of the LWLA1034 has a bug in the reset logic which
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* sometimes causes the response endpoint to be limited to transfers of
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* 64 bytes at a time, instead of the expected 2*512 bytes. The problem
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* can be worked around by never requesting more than 64 bytes.
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* This quirk manifests itself only under certain conditions, and some
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* users seem to see it more frequently than others. Detect it here in
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* order to avoid paying the penalty unnecessarily.
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*/
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static int detect_short_transfer_quirk(const struct sr_dev_inst *sdi)
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{
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struct dev_context *devc;
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struct sr_usb_dev_inst *usb;
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int xfer_len;
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int ret;
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uint16_t command[3];
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unsigned char buf[512];
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const int lreg_count = 10;
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devc = sdi->priv;
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usb = sdi->conn;
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command[0] = LWLA_WORD(CMD_READ_LREGS);
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command[1] = LWLA_WORD(0);
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command[2] = LWLA_WORD(lreg_count);
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ret = lwla_send_command(usb, command, ARRAY_SIZE(command));
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if (ret != SR_OK)
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return ret;
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ret = lwla_receive_reply(usb, buf, sizeof(buf), &xfer_len);
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if (ret != SR_OK)
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return ret;
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devc->short_transfer_quirk = (xfer_len == 64);
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if (xfer_len == 8 * lreg_count)
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return SR_OK;
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if (xfer_len == 64) {
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/* Drain the tailing portion of the split transfer. */
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ret = lwla_receive_reply(usb, buf, sizeof(buf), &xfer_len);
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if (ret != SR_OK)
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return ret;
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if (xfer_len == 8 * lreg_count - 64)
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return SR_OK;
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}
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sr_err("Received response of unexpected length %d.", xfer_len);
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return SR_ERR;
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}
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/* Select and transfer FPGA bitstream for the current configuration.
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*/
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static int apply_fpga_config(const struct sr_dev_inst *sdi)
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@ -317,7 +371,8 @@ static int device_init_check(const struct sr_dev_inst *sdi)
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sr_err("Received invalid test word 0x%016" PRIX64 ".", value);
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return SR_ERR;
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}
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return SR_OK;
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return detect_short_transfer_quirk(sdi);
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}
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/* Set up the device in preparation for an acquisition session.
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@ -404,7 +459,7 @@ static int prepare_request(const struct sr_dev_inst *sdi)
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{
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struct dev_context *devc;
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struct acquisition_state *acq;
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unsigned int count;
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unsigned int chunk_len, remaining, count;
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devc = sdi->priv;
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acq = devc->acquisition;
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@ -439,9 +494,12 @@ static int prepare_request(const struct sr_dev_inst *sdi)
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lwla_queue_regval(acq, REG_MEM_FILL, 0);
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break;
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case STATE_READ_REQUEST:
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/* Limit reads to 8 device words (36 bytes) at a time if the
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* device firmware has the short transfer quirk. */
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chunk_len = (devc->short_transfer_quirk) ? 8 : READ_CHUNK_LEN;
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/* Always read a multiple of 8 device words. */
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count = MIN(READ_CHUNK_LEN36, acq->mem_addr_stop
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- acq->mem_addr_next + 7) / 8 * 8;
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remaining = (acq->mem_addr_stop - acq->mem_addr_next + 7) / 8 * 8;
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count = MIN(chunk_len, remaining);
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acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM36);
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acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
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@ -129,6 +129,7 @@ struct dev_context {
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const struct model_info *model; /* device model descriptor */
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struct acquisition_state *acquisition; /* running capture state */
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int active_fpga_config; /* FPGA configuration index */
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gboolean short_transfer_quirk; /* 64 bytes response limit */
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enum protocol_state state; /* async protocol state */
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gboolean cancel_requested; /* stop after current transfer */
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