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asix-sigma: sync FPGA register names with documentation 

Rename source code identifiers for FPGA registers to closer match the
vendor's documentation.
This commit is contained in:
Gerhard Sittig 2020-05-09 17:16:13 +02:00
parent dc0906e21c
commit 9fb4c6324d
3 changed files with 12 additions and 11 deletions
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6
src/hardware/asix-sigma/api.c
View File

@ -412,12 +412,12 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
} }
/* Enter trigger programming mode. */ /* Enter trigger programming mode. */
sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); sigma_set_register(WRITE_TRIGGER_SELECT2, 0x20, devc);
triggerselect = 0; triggerselect = 0;
if (devc->cur_samplerate >= SR_MHZ(100)) { if (devc->cur_samplerate >= SR_MHZ(100)) {
/* 100 and 200 MHz mode. */ /* 100 and 200 MHz mode. */
sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); sigma_set_register(WRITE_TRIGGER_SELECT2, 0x81, devc);
/* Find which pin to trigger on from mask. */ /* Find which pin to trigger on from mask. */
for (triggerpin = 0; triggerpin < 8; triggerpin++) for (triggerpin = 0; triggerpin < 8; triggerpin++)
@ -451,7 +451,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
sizeof(struct triggerinout), devc); sizeof(struct triggerinout), devc);
/* Go back to normal mode. */ /* Go back to normal mode. */
sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); sigma_set_register(WRITE_TRIGGER_SELECT2, triggerselect, devc);
/* Set clock select register. */ /* Set clock select register. */
clockselect.async = 0; clockselect.async = 0;

6
src/hardware/asix-sigma/protocol.c
View File

@ -250,13 +250,13 @@ SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *
if (lut->m1d[3] & bit) if (lut->m1d[3] & bit)
tmp[1] |= 0x80; tmp[1] |= 0x80;
sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), sigma_write_register(WRITE_TRIGGER_SELECT, tmp, sizeof(tmp),
devc); devc);
sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); sigma_set_register(WRITE_TRIGGER_SELECT2, 0x30 | i, devc);
} }
/* Send the parameters */ /* Send the parameters */
sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, sigma_write_register(WRITE_TRIGGER_SELECT, (uint8_t *) &lut->params,
sizeof(lut->params), devc); sizeof(lut->params), devc);
return SR_OK; return SR_OK;

11
src/hardware/asix-sigma/protocol.h
View File

@ -55,14 +55,14 @@ enum asix_device_type {
enum sigma_write_register { enum sigma_write_register {
WRITE_CLOCK_SELECT = 0, WRITE_CLOCK_SELECT = 0,
WRITE_TRIGGER_SELECT0 = 1, WRITE_TRIGGER_SELECT = 1,
WRITE_TRIGGER_SELECT1 = 2, WRITE_TRIGGER_SELECT2 = 2,
WRITE_MODE = 3, WRITE_MODE = 3,
WRITE_MEMROW = 4, WRITE_MEMROW = 4,
WRITE_POST_TRIGGER = 5, WRITE_POST_TRIGGER = 5,
WRITE_TRIGGER_OPTION = 6, WRITE_TRIGGER_OPTION = 6,
WRITE_PIN_VIEW = 7, WRITE_PIN_VIEW = 7,
/* Unassigned register locations. */
WRITE_TEST = 15, WRITE_TEST = 15,
}; };
@ -79,8 +79,9 @@ enum sigma_read_register {
READ_PIN_CHANGE_HIGH = 9, READ_PIN_CHANGE_HIGH = 9,
READ_BLOCK_LAST_TS_LOW = 10, READ_BLOCK_LAST_TS_LOW = 10,
READ_BLOCK_LAST_TS_HIGH = 11, READ_BLOCK_LAST_TS_HIGH = 11,
READ_PIN_VIEW = 12, READ_BLOCK_TS_OVERRUN = 12,
READ_PIN_VIEW = 13,
/* Unassigned register location. */
READ_TEST = 15, READ_TEST = 15,
}; };