pipistrello-ols: Preliminary port to current API.
This commit is contained in:
parent
b94cff407f
commit
acc885c755
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@ -22,7 +22,7 @@
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static const int32_t hwcaps[] = {
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static const int32_t hwcaps[] = {
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SR_CONF_LOGIC_ANALYZER,
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SR_CONF_LOGIC_ANALYZER,
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SR_CONF_SAMPLERATE,
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SR_CONF_SAMPLERATE,
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SR_CONF_TRIGGER_TYPE,
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SR_CONF_TRIGGER_MATCH,
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SR_CONF_CAPTURE_RATIO,
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SR_CONF_CAPTURE_RATIO,
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SR_CONF_LIMIT_SAMPLES,
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SR_CONF_LIMIT_SAMPLES,
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SR_CONF_PATTERN_MODE,
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SR_CONF_PATTERN_MODE,
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@ -31,6 +31,13 @@ static const int32_t hwcaps[] = {
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SR_CONF_RLE,
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SR_CONF_RLE,
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};
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};
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static const int32_t trigger_matches[] = {
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SR_TRIGGER_ZERO,
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SR_TRIGGER_ONE,
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SR_TRIGGER_RISING,
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SR_TRIGGER_FALLING,
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};
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#define STR_PATTERN_NONE "None"
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#define STR_PATTERN_NONE "None"
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#define STR_PATTERN_EXTERNAL "External"
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#define STR_PATTERN_EXTERNAL "External"
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#define STR_PATTERN_INTERNAL "Internal"
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#define STR_PATTERN_INTERNAL "Internal"
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@ -184,8 +191,6 @@ static GSList *scan(GSList *options)
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if (p_ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
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if (p_ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
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sr_dbg("Failed to set default samplerate (%"PRIu64").",
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sr_dbg("Failed to set default samplerate (%"PRIu64").",
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DEFAULT_SAMPLERATE);
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DEFAULT_SAMPLERATE);
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/* Clear trigger masks, values and stages. */
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p_ols_configure_channels(sdi);
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drvc->instances = g_slist_append(drvc->instances, sdi);
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drvc->instances = g_slist_append(drvc->instances, sdi);
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devices = g_slist_append(devices, sdi);
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devices = g_slist_append(devices, sdi);
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@ -376,7 +381,7 @@ static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
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struct dev_context *devc;
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struct dev_context *devc;
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GVariant *gvar, *grange[2];
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GVariant *gvar, *grange[2];
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GVariantBuilder gvb;
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GVariantBuilder gvb;
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int num_channels, i;
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int num_pols_changrp, i;
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(void)cg;
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(void)cg;
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@ -392,8 +397,10 @@ static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
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g_variant_builder_add(&gvb, "{sv}", "samplerate-steps", gvar);
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g_variant_builder_add(&gvb, "{sv}", "samplerate-steps", gvar);
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*data = g_variant_builder_end(&gvb);
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*data = g_variant_builder_end(&gvb);
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break;
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break;
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case SR_CONF_TRIGGER_TYPE:
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case SR_CONF_TRIGGER_MATCH:
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*data = g_variant_new_string(TRIGGER_TYPE);
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*data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
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trigger_matches, ARRAY_SIZE(trigger_matches),
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sizeof(int32_t));
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break;
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break;
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case SR_CONF_PATTERN_MODE:
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case SR_CONF_PATTERN_MODE:
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*data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns));
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*data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns));
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@ -411,23 +418,20 @@ static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
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* Channel groups are turned off if no channels in that group are
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* Channel groups are turned off if no channels in that group are
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* enabled, making more room for samples for the enabled group.
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* enabled, making more room for samples for the enabled group.
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*/
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*/
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p_ols_configure_channels(sdi);
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pols_channel_mask(sdi);
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num_channels = 0;
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num_pols_changrp = 0;
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for (i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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if (devc->channel_mask & (0xff << (i * 8)))
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if (devc->channel_mask & (0xff << (i * 8)))
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num_channels++;
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num_pols_changrp++;
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}
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if (num_channels == 0) {
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/* This can happen, but shouldn't cause too much drama.
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* However we can't continue because the code below would
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* divide by zero. */
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break;
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}
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}
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/* 3 channel groups takes as many bytes as 4 channel groups */
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/* 3 channel groups takes as many bytes as 4 channel groups */
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if (num_channels == 3)
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if (num_pols_changrp == 3)
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num_channels = 4;
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num_pols_changrp = 4;
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grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
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grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
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grange[1] = g_variant_new_uint64(devc->max_samplebytes / num_channels);
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if (num_pols_changrp)
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grange[1] = g_variant_new_uint64(devc->max_samplebytes / num_pols_changrp);
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else
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grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES);
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*data = g_variant_new_tuple(grange, 2);
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*data = g_variant_new_tuple(grange, 2);
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break;
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break;
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default:
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default:
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@ -520,9 +524,9 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi,
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{
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{
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struct dev_context *devc;
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struct dev_context *devc;
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uint32_t samplecount, readcount, delaycount;
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uint32_t samplecount, readcount, delaycount;
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uint8_t changrp_mask, arg[4];
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uint8_t pols_changrp_mask, arg[4];
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uint16_t flag_tmp;
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uint16_t flag_tmp;
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int num_channels, samplespercount;
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int num_pols_changrp, samplespercount;
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int ret, i;
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int ret, i;
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if (sdi->status != SR_ST_ACTIVE)
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if (sdi->status != SR_ST_ACTIVE)
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@ -530,29 +534,26 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi,
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devc = sdi->priv;
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devc = sdi->priv;
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if (p_ols_configure_channels(sdi) != SR_OK) {
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pols_channel_mask(sdi);
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sr_err("Failed to configure channels.");
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return SR_ERR;
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}
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/*
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/*
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* Enable/disable channel groups in the flag register according to the
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* Enable/disable channel groups in the flag register according to the
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* channel mask. Calculate this here, because num_channels is needed
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* channel mask. Calculate this here, because num_pols_changrp is
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* to limit readcount.
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* needed to limit readcount.
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*/
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*/
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changrp_mask = 0;
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pols_changrp_mask = 0;
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num_channels = 0;
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num_pols_changrp = 0;
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for (i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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if (devc->channel_mask & (0xff << (i * 8))) {
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if (devc->channel_mask & (0xff << (i * 8))) {
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changrp_mask |= (1 << i);
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pols_changrp_mask |= (1 << i);
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num_channels++;
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num_pols_changrp++;
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}
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}
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}
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}
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/* 3 channel groups takes as many bytes as 4 channel groups */
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/* 3 channel groups takes as many bytes as 4 channel groups */
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if (num_channels == 3)
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if (num_pols_changrp == 3)
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num_channels = 4;
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num_pols_changrp = 4;
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/* maximum number of samples (or RLE counts) the buffer memory can hold */
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/* maximum number of samples (or RLE counts) the buffer memory can hold */
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devc->max_samples = devc->max_samplebytes / num_channels;
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devc->max_samples = devc->max_samplebytes / num_pols_changrp;
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/*
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/*
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* Limit readcount to prevent reading past the end of the hardware
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* Limit readcount to prevent reading past the end of the hardware
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@ -578,12 +579,15 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi,
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readcount++;
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readcount++;
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/* Basic triggers. */
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/* Basic triggers. */
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if (devc->trigger_mask[0] != 0x00000000) {
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if (pols_convert_trigger(sdi) != SR_OK) {
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/* At least one channel has a trigger on it. */
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sr_err("Failed to configure channels.");
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return SR_ERR;
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}
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if (devc->num_stages > 0) {
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delaycount = readcount * (1 - devc->capture_ratio / 100.0);
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delaycount = readcount * (1 - devc->capture_ratio / 100.0);
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devc->trigger_at = (readcount - delaycount) * samplespercount - devc->num_stages;
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devc->trigger_at = (readcount - delaycount) * samplespercount - devc->num_stages;
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for (i = 0; i <= devc->num_stages; i++) {
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for (i = 0; i <= devc->num_stages; i++) {
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sr_dbg("Setting stage %d trigger.", i);
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sr_dbg("Setting p-ols stage %d trigger.", i);
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if ((ret = set_trigger(sdi, i)) != SR_OK)
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if ((ret = set_trigger(sdi, i)) != SR_OK)
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return ret;
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return ret;
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}
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}
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@ -604,6 +608,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi,
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arg[3] = 0x00;
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arg[3] = 0x00;
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if (write_longcommand(devc, CMD_SET_DIVIDER, arg) != SR_OK)
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if (write_longcommand(devc, CMD_SET_DIVIDER, arg) != SR_OK)
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return SR_ERR;
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return SR_ERR;
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/* Send extended sample limit and pre/post-trigger capture ratio. */
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/* Send extended sample limit and pre/post-trigger capture ratio. */
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arg[0] = ((readcount - 1) & 0xff);
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arg[0] = ((readcount - 1) & 0xff);
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arg[1] = ((readcount - 1) & 0xff00) >> 8;
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arg[1] = ((readcount - 1) & 0xff00) >> 8;
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@ -617,6 +622,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi,
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arg[3] = ((delaycount - 1) & 0xff000000) >> 24;
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arg[3] = ((delaycount - 1) & 0xff000000) >> 24;
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if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK)
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if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK)
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return SR_ERR;
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return SR_ERR;
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/* Flag register. */
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/* Flag register. */
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sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
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sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
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devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
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devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
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@ -630,7 +636,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi,
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* to the channel mask. 1 means "disable channel".
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* to the channel mask. 1 means "disable channel".
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*/
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*/
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devc->flag_reg &= ~0x3c;
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devc->flag_reg &= ~0x3c;
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devc->flag_reg |= ~(changrp_mask << 2) & 0x3c;
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devc->flag_reg |= ~(pols_changrp_mask << 2) & 0x3c;
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sr_dbg("flag_reg = %x", devc->flag_reg);
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sr_dbg("flag_reg = %x", devc->flag_reg);
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/*
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/*
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@ -641,7 +647,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi,
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flag_tmp = devc->flag_reg;
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flag_tmp = devc->flag_reg;
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if (devc->flag_reg & FLAG_DEMUX) {
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if (devc->flag_reg & FLAG_DEMUX) {
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flag_tmp &= ~0x30;
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flag_tmp &= ~0x30;
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flag_tmp |= ~(changrp_mask << 4) & 0x30;
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flag_tmp |= ~(pols_changrp_mask << 4) & 0x30;
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}
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}
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arg[0] = flag_tmp & 0xff;
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arg[0] = flag_tmp & 0xff;
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arg[1] = flag_tmp >> 8;
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arg[1] = flag_tmp >> 8;
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@ -663,7 +669,8 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi,
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std_session_send_df_header(cb_data, LOG_PREFIX);
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std_session_send_df_header(cb_data, LOG_PREFIX);
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/* Hook up a dummy handler to receive data from the device. */
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/* Hook up a dummy handler to receive data from the device. */
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sr_source_add(-1, G_IO_IN, 0, p_ols_receive_data, (void *)sdi);
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sr_session_source_add(sdi->session, 0, G_IO_IN, 10, p_ols_receive_data,
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cb_data);
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return SR_OK;
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return SR_OK;
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}
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}
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@ -684,7 +691,7 @@ static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
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write_shortcommand(devc, CMD_RESET);
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write_shortcommand(devc, CMD_RESET);
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write_shortcommand(devc, CMD_RESET);
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write_shortcommand(devc, CMD_RESET);
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sr_source_remove(-1);
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sr_session_source_remove(sdi->session, 0);
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/* Send end packet to the session bus. */
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/* Send end packet to the session bus. */
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sr_dbg("Sending SR_DF_END.");
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sr_dbg("Sending SR_DF_END.");
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@ -695,7 +702,7 @@ static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
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}
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}
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SR_PRIV struct sr_dev_driver p_ols_driver_info = {
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SR_PRIV struct sr_dev_driver p_ols_driver_info = {
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.name = "p_ols",
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.name = "p-ols",
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.longname = "Pipistrello OLS",
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.longname = "Pipistrello OLS",
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.api_version = 1,
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.api_version = 1,
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.init = init,
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.init = init,
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@ -153,59 +153,64 @@ SR_PRIV int p_ols_close(struct dev_context *devc)
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return SR_OK;
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return SR_OK;
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}
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}
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SR_PRIV int p_ols_configure_channels(const struct sr_dev_inst *sdi)
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/* Configures the channel mask based on which channels are enabled. */
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SR_PRIV void pols_channel_mask(const struct sr_dev_inst *sdi)
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{
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{
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struct dev_context *devc;
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struct dev_context *devc;
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const struct sr_channel *ch;
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struct sr_channel *channel;
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const GSList *l;
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const GSList *l;
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int channel_bit, stage, i;
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char *tc;
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devc = sdi->priv;
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devc = sdi->priv;
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devc->channel_mask = 0;
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devc->channel_mask = 0;
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for (l = sdi->channels; l; l = l->next) {
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channel = l->data;
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if (channel->enabled)
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devc->channel_mask |= 1 << channel->index;
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}
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}
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SR_PRIV int pols_convert_trigger(const struct sr_dev_inst *sdi)
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{
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struct dev_context *devc;
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struct sr_trigger *trigger;
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struct sr_trigger_stage *stage;
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struct sr_trigger_match *match;
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const GSList *l, *m;
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int i;
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devc = sdi->priv;
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devc->num_stages = 0;
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for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
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for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
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devc->trigger_mask[i] = 0;
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devc->trigger_mask[i] = 0;
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devc->trigger_value[i] = 0;
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devc->trigger_value[i] = 0;
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devc->trigger_edge[i] = 0;
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devc->trigger_edge[i] = 0;
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}
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}
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devc->num_stages = 0;
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if (!(trigger = sr_session_trigger_get(sdi->session)))
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for (l = sdi->channels; l; l = l->next) {
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return SR_OK;
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ch = (const struct sr_channel *)l->data;
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if (!ch->enabled)
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continue;
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if (ch->index >= devc->max_channels) {
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devc->num_stages = g_slist_length(trigger->stages);
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sr_err("Channels over the limit of %d\n", devc->max_channels);
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if (devc->num_stages > NUM_TRIGGER_STAGES) {
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return SR_ERR;
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sr_err("This device only supports %d trigger stages.",
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NUM_TRIGGER_STAGES);
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return SR_ERR;
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}
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for (l = trigger->stages; l; l = l->next) {
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stage = l->data;
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for (m = stage->matches; m; m = m->next) {
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match = m->data;
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if (!match->channel->enabled)
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/* Ignore disabled channels with a trigger. */
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continue;
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devc->trigger_mask[stage->stage] |= 1 << match->channel->index;
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if (match->match == SR_TRIGGER_ONE || match->match == SR_TRIGGER_RISING)
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devc->trigger_value[stage->stage] |= 1 << match->channel->index;
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if (match->match == SR_TRIGGER_RISING || match->match == SR_TRIGGER_FALLING)
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devc->trigger_edge[stage->stage] |= 1 << match->channel->index;
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}
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}
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/*
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* Set up the channel mask for later configuration into the
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* flag register.
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*/
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channel_bit = 1 << (ch->index);
|
|
||||||
devc->channel_mask |= channel_bit;
|
|
||||||
|
|
||||||
if (!ch->trigger)
|
|
||||||
continue;
|
|
||||||
|
|
||||||
/* Configure trigger mask and value. */
|
|
||||||
stage = 0;
|
|
||||||
for (tc = ch->trigger; tc && *tc; tc++) {
|
|
||||||
devc->trigger_mask[stage] |= channel_bit;
|
|
||||||
if ((*tc == '1') || (*tc == 'r'))
|
|
||||||
devc->trigger_value[stage] |= channel_bit;
|
|
||||||
if ((*tc == 'r') || (*tc == 'f'))
|
|
||||||
devc->trigger_edge[stage] |= channel_bit;
|
|
||||||
stage++;
|
|
||||||
/* Only supporting parallel mode, with up to 4 stages. */
|
|
||||||
if (stage > 3)
|
|
||||||
return SR_ERR;
|
|
||||||
}
|
|
||||||
if (stage > devc->num_stages)
|
|
||||||
devc->num_stages = stage - 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return SR_OK;
|
return SR_OK;
|
||||||
|
|
|
@ -32,14 +32,13 @@
|
||||||
#include "libsigrok.h"
|
#include "libsigrok.h"
|
||||||
#include "libsigrok-internal.h"
|
#include "libsigrok-internal.h"
|
||||||
|
|
||||||
#define LOG_PREFIX "pipistrello_ols"
|
#define LOG_PREFIX "p-ols"
|
||||||
|
|
||||||
#define FTDI_BUF_SIZE (16 * 1024)
|
#define FTDI_BUF_SIZE (16 * 1024)
|
||||||
|
|
||||||
|
|
||||||
#define NUM_CHANNELS 32
|
#define NUM_CHANNELS 32
|
||||||
#define NUM_TRIGGER_STAGES 4
|
#define NUM_TRIGGER_STAGES 4
|
||||||
#define TRIGGER_TYPE "01rf"
|
|
||||||
#define CLOCK_RATE SR_MHZ(100)
|
#define CLOCK_RATE SR_MHZ(100)
|
||||||
#define MIN_NUM_SAMPLES 4
|
#define MIN_NUM_SAMPLES 4
|
||||||
#define DEFAULT_SAMPLERATE SR_MHZ(100)
|
#define DEFAULT_SAMPLERATE SR_MHZ(100)
|
||||||
|
@ -97,9 +96,9 @@ struct dev_context {
|
||||||
int capture_ratio;
|
int capture_ratio;
|
||||||
int trigger_at;
|
int trigger_at;
|
||||||
uint32_t channel_mask;
|
uint32_t channel_mask;
|
||||||
uint32_t trigger_mask[4];
|
uint32_t trigger_mask[NUM_TRIGGER_STAGES];
|
||||||
uint32_t trigger_value[4];
|
uint32_t trigger_value[NUM_TRIGGER_STAGES];
|
||||||
uint32_t trigger_edge[4];
|
uint32_t trigger_edge[NUM_TRIGGER_STAGES];
|
||||||
int num_stages;
|
int num_stages;
|
||||||
uint16_t flag_reg;
|
uint16_t flag_reg;
|
||||||
|
|
||||||
|
@ -125,7 +124,8 @@ SR_PRIV int write_shortcommand(struct dev_context *devc, uint8_t command);
|
||||||
SR_PRIV int write_longcommand(struct dev_context *devc, uint8_t command, uint8_t *data);
|
SR_PRIV int write_longcommand(struct dev_context *devc, uint8_t command, uint8_t *data);
|
||||||
SR_PRIV int p_ols_open(struct dev_context *devc);
|
SR_PRIV int p_ols_open(struct dev_context *devc);
|
||||||
SR_PRIV int p_ols_close(struct dev_context *devc);
|
SR_PRIV int p_ols_close(struct dev_context *devc);
|
||||||
SR_PRIV int p_ols_configure_channels(const struct sr_dev_inst *sdi);
|
SR_PRIV void pols_channel_mask(const struct sr_dev_inst *sdi);
|
||||||
|
SR_PRIV int pols_convert_trigger(const struct sr_dev_inst *sdi);
|
||||||
SR_PRIV struct sr_dev_inst *p_ols_get_metadata(uint8_t *buf, int bytes_read, struct dev_context *devc);
|
SR_PRIV struct sr_dev_inst *p_ols_get_metadata(uint8_t *buf, int bytes_read, struct dev_context *devc);
|
||||||
SR_PRIV int p_ols_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate);
|
SR_PRIV int p_ols_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate);
|
||||||
SR_PRIV int p_ols_receive_data(int fd, int revents, void *cb_data);
|
SR_PRIV int p_ols_receive_data(int fd, int revents, void *cb_data);
|
||||||
|
|
Loading…
Reference in New Issue