chronovu-la: Use new trigger API.
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@ -26,11 +26,18 @@ static struct sr_dev_driver *di = &chronovu_la_driver_info;
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static const int32_t hwcaps[] = {
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SR_CONF_LOGIC_ANALYZER,
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SR_CONF_SAMPLERATE,
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SR_CONF_TRIGGER_TYPE,
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SR_CONF_TRIGGER_MATCH,
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SR_CONF_LIMIT_MSEC, /* TODO: Not yet implemented. */
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SR_CONF_LIMIT_SAMPLES, /* TODO: Not yet implemented. */
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};
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static const int32_t trigger_matches[] = {
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SR_TRIGGER_ZERO,
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SR_TRIGGER_ONE,
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SR_TRIGGER_RISING,
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SR_TRIGGER_FALLING,
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};
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/* The ChronoVu LA8/LA16 can have multiple VID/PID pairs. */
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static struct {
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uint16_t vid;
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@ -369,10 +376,11 @@ static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
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grange[1] = g_variant_new_uint64(MAX_NUM_SAMPLES / 2);
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*data = g_variant_new_tuple(grange, 2);
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break;
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case SR_CONF_TRIGGER_TYPE:
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case SR_CONF_TRIGGER_MATCH:
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if (!sdi || !sdi->priv || !(devc = sdi->priv) || !devc->prof)
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return SR_ERR_BUG;
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*data = g_variant_new_string(devc->prof->trigger_type);
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*data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
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trigger_matches, devc->prof->num_trigger_matches,
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sizeof(int32_t));
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break;
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default:
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return SR_ERR_NA;
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@ -461,8 +469,8 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
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return SR_ERR;
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}
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if (cv_configure_channels(sdi) != SR_OK) {
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sr_err("Failed to configure channels.");
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if (cv_convert_trigger(sdi) != SR_OK) {
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sr_err("Failed to configure trigger.");
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return SR_ERR;
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}
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@ -21,11 +21,9 @@
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#include "protocol.h"
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SR_PRIV const struct cv_profile cv_profiles[] = {
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{ CHRONOVU_LA8, "LA8", "ChronoVu LA8", 8, SR_MHZ(100), "01",
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0.8388608 },
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{ CHRONOVU_LA16, "LA16", "ChronoVu LA16", 16, SR_MHZ(200), "01rf",
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0.042 },
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{ 0, NULL, NULL, 0, 0, NULL, 0.0 },
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{ CHRONOVU_LA8, "LA8", "ChronoVu LA8", 8, SR_MHZ(100), 2, 0.8388608 },
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{ CHRONOVU_LA16, "LA16", "ChronoVu LA16", 16, SR_MHZ(200), 4, 0.042 },
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{ 0, NULL, NULL, 0, 0, 0, 0.0 },
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};
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/* LA8: channels are numbered 0-7. LA16: channels are numbered 0-15. */
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@ -260,73 +258,60 @@ static int reset_device(struct dev_context *devc)
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return SR_OK;
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}
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SR_PRIV int cv_configure_channels(const struct sr_dev_inst *sdi)
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SR_PRIV int cv_convert_trigger(const struct sr_dev_inst *sdi)
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{
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struct dev_context *devc;
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const struct sr_channel *ch;
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const GSList *l;
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struct sr_trigger *trigger;
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struct sr_trigger_stage *stage;
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struct sr_trigger_match *match;
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const GSList *l, *m;
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uint16_t channel_bit;
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char *tc;
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devc = sdi->priv;
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devc->trigger_pattern = 0x0000; /* Default to "low" trigger. */
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devc->trigger_mask = 0x0000; /* Default to "don't care". */
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devc->trigger_edgemask = 0x0000; /* Default to "state triggered". */
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for (l = sdi->channels; l; l = l->next) {
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ch = (struct sr_channel *)l->data;
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if (!(trigger = sr_session_trigger_get()))
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return SR_OK;
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if (!ch) {
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sr_err("%s: channel was NULL.", __func__);
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return SR_ERR;
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}
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if (g_slist_length(trigger->stages) > 1) {
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sr_err("This device only supports 1 trigger stage.");
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return SR_ERR;
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}
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/* Skip disabled channels. */
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if (!ch->enabled)
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continue;
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/* Skip (enabled) channels with no configured trigger. */
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if (!ch->trigger)
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continue;
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/* Note: Must only be run if ch->trigger != NULL. */
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if (ch->index < 0 || ch->index > (int)devc->prof->num_channels - 1) {
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sr_err("Invalid channel index %d, must be "
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"between 0 and %d.", ch->index,
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devc->prof->num_channels - 1);
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return SR_ERR;
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}
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channel_bit = (1 << (ch->index));
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/* Configure the channel's trigger pattern/mask/edgemask. */
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for (tc = ch->trigger; tc && *tc; tc++) {
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devc->trigger_mask |= channel_bit;
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/* Sanity check, LA8 only supports low/high trigger. */
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if ((devc->prof->model == CHRONOVU_LA8) &&
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(*tc != '0' && *tc != '1')) {
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sr_err("Invalid trigger '%c', only "
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"'0'/'1' supported.", *tc);
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for (l = trigger->stages; l; l = l->next) {
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stage = l->data;
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for (m = stage->matches; m; m = m->next) {
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match = m->data;
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if (!match->channel->enabled)
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/* Ignore disabled channels with a trigger. */
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continue;
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if (devc->prof->model == CHRONOVU_LA8 &&
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(match->match == SR_TRIGGER_RISING
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|| match->match == SR_TRIGGER_FALLING)) {
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sr_err("This model supports only simple triggers.");
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return SR_ERR;
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}
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channel_bit = (1 << (match->channel->index));
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/* state: 1 == high, edge: 1 == rising edge. */
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if (*tc == '1' || *tc == 'r')
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if (match->match == SR_TRIGGER_ONE
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|| match->match == SR_TRIGGER_RISING)
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devc->trigger_pattern |= channel_bit;
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/* LA16 (but not LA8) supports edge triggering. */
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if ((devc->prof->model == CHRONOVU_LA16)) {
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if (*tc == 'r' || *tc == 'f')
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devc->trigger_edgemask |= channel_bit;
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if (match->match == SR_TRIGGER_RISING
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|| match->match == SR_TRIGGER_FALLING)
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devc->trigger_edgemask |= channel_bit;
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}
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}
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}
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sr_dbg("Trigger pattern/mask/edgemask = 0x%04x / 0x%04x / 0x%04x.",
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devc->trigger_pattern, devc->trigger_mask,
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devc->trigger_edgemask);
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devc->trigger_pattern, devc->trigger_mask,
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devc->trigger_edgemask);
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return SR_OK;
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}
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@ -47,7 +47,7 @@ struct cv_profile {
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const char *iproduct; /* USB iProduct string */
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unsigned int num_channels;
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uint64_t max_samplerate;
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const char *trigger_type;
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const int num_trigger_matches;
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float trigger_constant;
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};
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@ -133,7 +133,7 @@ SR_PRIV void cv_fill_samplerates_if_needed(const struct sr_dev_inst *sdi);
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SR_PRIV uint8_t cv_samplerate_to_divcount(const struct sr_dev_inst *sdi,
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uint64_t samplerate);
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SR_PRIV int cv_write(struct dev_context *devc, uint8_t *buf, int size);
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SR_PRIV int cv_configure_channels(const struct sr_dev_inst *sdi);
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SR_PRIV int cv_convert_trigger(const struct sr_dev_inst *sdi);
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SR_PRIV int cv_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate);
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SR_PRIV int cv_read_block(struct dev_context *devc);
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SR_PRIV void cv_send_block_to_session_bus(struct dev_context *devc, int block);
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