fx2lafw: Basic acquisition support for DSLogic.
This commit is contained in:
Bert Vermeulen
Uwe Hermann
parent
0e6510b8fc
commit
b9d530920f
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@ -225,7 +225,8 @@ libsigrok_la_SOURCES += \
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src/hardware/fx2lafw/protocol.h \
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src/hardware/fx2lafw/protocol.c \
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src/hardware/fx2lafw/api.c \
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src/hardware/fx2lafw/dslogic.c
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src/hardware/fx2lafw/dslogic.c \
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src/hardware/fx2lafw/dslogic.h
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endif
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if HW_GMC_MH_1X_2X
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libsigrok_la_SOURCES += \
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@ -1,91 +0,0 @@
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/*
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* This file is part of the libsigrok project.
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*
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* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
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* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <unistd.h>
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#include <errno.h>
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#include <glib.h>
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#include <glib/gstdio.h>
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#include "protocol.h"
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#define FW_BUFSIZE 4096
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int dslogic_fpga_firmware_upload(struct libusb_device_handle *hdl,
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const char *filename)
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{
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FILE *fw;
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struct stat st;
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int chunksize, result, ret;
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unsigned char *buf;
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int sum, transferred;
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sr_info("Uploading FPGA firmware at %s.", filename);
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if (stat(filename, &st) < 0) {
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sr_err("Unable to upload FPGA firmware: %s", strerror(errno));
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return SR_ERR;
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}
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/* Tell the device firmware is coming. */
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if ((ret = libusb_control_transfer(hdl, LIBUSB_REQUEST_TYPE_VENDOR |
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LIBUSB_ENDPOINT_OUT, CMD_DSLOGIC_CONFIG, 0x0000, 0x0000,
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NULL, 0, 3000)) < 0) {
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sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
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return SR_ERR;
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}
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buf = g_malloc(FW_BUFSIZE);
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if ((fw = g_fopen(filename, "rb")) == NULL) {
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sr_err("Unable to open %s for reading: %s.", filename, strerror(errno));
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return SR_ERR;
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}
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/* Give the FX2 time to get ready for FPGA firmware upload. */
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g_usleep(10 * 1000);
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sum = 0;
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result = SR_OK;
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while (1) {
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if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0)
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break;
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if ((ret = libusb_bulk_transfer(hdl, 2 | LIBUSB_ENDPOINT_OUT,
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buf, chunksize, &transferred, 1000)) < 0) {
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sr_err("Unable to configure FPGA firmware: %s.",
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libusb_error_name(ret));
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result = SR_ERR;
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break;
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}
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sum += transferred;
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sr_info("Uploaded %d/%d bytes.", sum, st.st_size);
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if (transferred != chunksize) {
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sr_err("Short transfer while uploading FPGA firmware.");
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result = SR_ERR;
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break;
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}
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}
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fclose(fw);
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if (result == SR_OK)
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sr_info("FPGA firmware upload done.");
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return result;
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}
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@ -19,6 +19,7 @@
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*/
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#include "protocol.h"
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#include "dslogic.h"
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static const struct fx2lafw_profile supported_fx2[] = {
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/*
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@ -411,7 +412,7 @@ static int dev_open(struct sr_dev_inst *sdi)
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}
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if (devc->dslogic) {
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if ((ret = dslogic_fpga_firmware_upload(usb->devhdl,
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if ((ret = dslogic_fpga_firmware_upload(sdi,
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DSLOGIC_FPGA_FIRMWARE)) != SR_OK)
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return ret;
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}
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@ -611,22 +612,17 @@ static int receive_data(int fd, int revents, void *cb_data)
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return TRUE;
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}
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static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
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static int start_transfers(const struct sr_dev_inst *sdi)
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{
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struct dev_context *devc;
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struct drv_context *drvc;
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struct sr_usb_dev_inst *usb;
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struct sr_trigger *trigger;
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struct libusb_transfer *transfer;
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unsigned int i, timeout, num_transfers;
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int ret;
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unsigned int i, num_transfers;
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int endpoint, timeout, ret;
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unsigned char *buf;
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size_t size;
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if (sdi->status != SR_ST_ACTIVE)
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return SR_ERR_DEV_CLOSED;
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drvc = di->priv;
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devc = sdi->priv;
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usb = sdi->conn;
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@ -647,6 +643,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
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devc->trigger_fired = TRUE;
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timeout = fx2lafw_get_timeout(devc);
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num_transfers = fx2lafw_get_number_of_transfers(devc);
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size = fx2lafw_get_buffer_size(devc);
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devc->submitted_transfers = 0;
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@ -657,6 +654,8 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
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return SR_ERR_MALLOC;
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}
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timeout = fx2lafw_get_timeout(devc);
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endpoint = devc->dslogic ? 6 : 2;
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devc->num_transfers = num_transfers;
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for (i = 0; i < num_transfers; i++) {
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if (!(buf = g_try_malloc(size))) {
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@ -665,7 +664,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
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}
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transfer = libusb_alloc_transfer(0);
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libusb_fill_bulk_transfer(transfer, usb->devhdl,
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2 | LIBUSB_ENDPOINT_IN, buf, size,
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endpoint | LIBUSB_ENDPOINT_IN, buf, size,
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fx2lafw_receive_transfer, (void *)sdi, timeout);
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if ((ret = libusb_submit_transfer(transfer)) != 0) {
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sr_err("Failed to submit transfer: %s.",
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@ -679,16 +678,101 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
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devc->submitted_transfers++;
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}
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devc->ctx = drvc->sr_ctx;
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/* Send header packet to the session bus. */
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std_session_send_df_header(devc->cb_data, LOG_PREFIX);
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usb_source_add(sdi->session, devc->ctx, timeout, receive_data, NULL);
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/* Send header packet to the session bus. */
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std_session_send_df_header(cb_data, LOG_PREFIX);
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return SR_OK;
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}
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if ((ret = fx2lafw_command_start_acquisition(sdi)) != SR_OK) {
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fx2lafw_abort_acquisition(devc);
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static void dslogic_trigger_receive(struct libusb_transfer *transfer)
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{
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const struct sr_dev_inst *sdi;
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struct dslogic_trigger_pos *tpos;
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sdi = transfer->user_data;
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if (transfer->status == LIBUSB_TRANSFER_COMPLETED
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&& transfer->actual_length == sizeof(struct dslogic_trigger_pos)) {
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tpos = (struct dslogic_trigger_pos *)transfer->buffer;
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sr_dbg("tpos real_pos %.8x ram_saddr %.8x", tpos->real_pos, tpos->ram_saddr);
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g_free(tpos);
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start_transfers(sdi);
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}
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libusb_free_transfer(transfer);
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}
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static int dslogic_trigger_request(const struct sr_dev_inst *sdi)
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{
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struct sr_usb_dev_inst *usb;
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struct libusb_transfer *transfer;
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struct dslogic_trigger_pos *tpos;
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int ret;
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usb = sdi->conn;
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if ((ret = dslogic_stop_acquisition(sdi)) != SR_OK)
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return ret;
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if ((ret = dslogic_fpga_configure(sdi)) != SR_OK)
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return ret;
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if ((ret = dslogic_start_acquisition(sdi)) != SR_OK)
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return ret;
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sr_dbg("Getting trigger.");
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tpos = g_malloc(sizeof(struct dslogic_trigger_pos));
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transfer = libusb_alloc_transfer(0);
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libusb_fill_bulk_transfer(transfer, usb->devhdl, 6 | LIBUSB_ENDPOINT_IN,
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(unsigned char *)tpos, sizeof(struct dslogic_trigger_pos),
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dslogic_trigger_receive, (void *)sdi, 0);
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if ((ret = libusb_submit_transfer(transfer)) < 0) {
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sr_err("Failed to request trigger: %s.", libusb_error_name(ret));
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libusb_free_transfer(transfer);
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g_free(tpos);
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return SR_ERR;
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}
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return ret;
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}
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static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
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{
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struct drv_context *drvc;
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struct dev_context *devc;
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int timeout, ret;
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if (sdi->status != SR_ST_ACTIVE)
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return SR_ERR_DEV_CLOSED;
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drvc = di->priv;
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devc = sdi->priv;
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/* Configures devc->trigger_* and devc->sample_wide */
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if (fx2lafw_configure_channels(sdi) != SR_OK) {
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sr_err("Failed to configure channels.");
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return SR_ERR;
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}
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devc->ctx = drvc->sr_ctx;
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devc->cb_data = cb_data;
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devc->sent_samples = 0;
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devc->empty_transfer_count = 0;
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devc->acq_aborted = FALSE;
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timeout = fx2lafw_get_timeout(devc);
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usb_source_add(devc->ctx, timeout, receive_data, NULL);
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if (devc->dslogic) {
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dslogic_trigger_request(sdi);
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}
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else {
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if ((ret = fx2lafw_command_start_acquisition(sdi)) != SR_OK)
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return ret;
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start_transfers(sdi);
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}
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return SR_OK;
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@ -0,0 +1,229 @@
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/*
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* This file is part of the libsigrok project.
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*
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* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
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* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <unistd.h>
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#include <errno.h>
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#include <math.h>
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#include <glib.h>
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#include <glib/gstdio.h>
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#include "protocol.h"
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#include "dslogic.h"
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#define FW_BUFSIZE 4096
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int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
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const char *filename)
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{
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FILE *fw;
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struct stat st;
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struct sr_usb_dev_inst *usb;
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int chunksize, result, ret;
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unsigned char *buf;
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int sum, transferred;
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sr_dbg("Uploading FPGA firmware at %s.", filename);
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usb = sdi->conn;
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if (stat(filename, &st) < 0) {
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sr_err("Unable to upload FPGA firmware: %s", strerror(errno));
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return SR_ERR;
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}
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/* Tell the device firmware is coming. */
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if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
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LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
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NULL, 0, 3000)) < 0) {
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sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
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return SR_ERR;
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}
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buf = g_malloc(FW_BUFSIZE);
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if ((fw = g_fopen(filename, "rb")) == NULL) {
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sr_err("Unable to open %s for reading: %s.", filename, strerror(errno));
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return SR_ERR;
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}
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/* Give the FX2 time to get ready for FPGA firmware upload. */
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g_usleep(10 * 1000);
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sum = 0;
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result = SR_OK;
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while (1) {
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if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0)
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break;
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if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
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buf, chunksize, &transferred, 1000)) < 0) {
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sr_err("Unable to configure FPGA firmware: %s.",
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libusb_error_name(ret));
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result = SR_ERR;
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break;
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}
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sum += transferred;
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sr_spew("Uploaded %d/%d bytes.", sum, st.st_size);
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if (transferred != chunksize) {
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sr_err("Short transfer while uploading FPGA firmware.");
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result = SR_ERR;
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break;
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}
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}
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fclose(fw);
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g_free(buf);
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if (result == SR_OK)
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sr_dbg("FPGA firmware upload done.");
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return result;
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}
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int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
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{
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struct dev_context *devc;
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struct sr_usb_dev_inst *usb;
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struct dslogic_mode mode;
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int ret;
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devc = sdi->priv;
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mode.flags = 0;
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mode.sample_delay_h = mode.sample_delay_l = 0;
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if (devc->sample_wide)
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mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;
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usb = sdi->conn;
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ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
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LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
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(unsigned char *)&mode, sizeof(mode), 3000);
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if (ret < 0) {
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sr_err("Failed to send start command: %s.", libusb_error_name(ret));
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return SR_ERR;
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}
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return SR_OK;
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}
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int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
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{
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struct sr_usb_dev_inst *usb;
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struct dslogic_mode mode;
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int ret;
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mode.flags = DS_START_FLAGS_STOP;
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mode.sample_delay_h = mode.sample_delay_l = 0;
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usb = sdi->conn;
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ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
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LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
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(unsigned char *)&mode, sizeof(struct dslogic_mode), 3000);
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if (ret < 0) {
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sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
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return SR_ERR;
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}
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return SR_OK;
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}
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int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
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{
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struct dev_context *devc;
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struct sr_usb_dev_inst *usb;
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uint8_t c[3];
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struct dslogic_fpga_config cfg;
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uint16_t v16;
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uint32_t v32;
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int transferred, len, ret;
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sr_dbg("Configuring FPGA.");
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usb = sdi->conn;
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devc = sdi->priv;
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WL32(&cfg.sync, DS_CFG_START);
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WL16(&cfg.mode_header, DS_CFG_MODE);
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WL32(&cfg.divider_header, DS_CFG_DIVIDER);
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WL32(&cfg.count_header, DS_CFG_COUNT);
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WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
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WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
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WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
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WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
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WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
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WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
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WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
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WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
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WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
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WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
|
||||
WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
|
||||
WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
|
||||
WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
|
||||
WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
|
||||
WL32(&cfg.end_sync, DS_CFG_END);
|
||||
|
||||
/* Pass in the length of a fixed-size struct. Really. */
|
||||
len = sizeof(struct dslogic_fpga_config) / 2;
|
||||
c[0] = len & 0xff;
|
||||
c[1] = (len >> 8) & 0xff;
|
||||
c[2] = (len >> 16) & 0xff;
|
||||
|
||||
ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
|
||||
LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
|
||||
c, 3, 100);
|
||||
if (ret < 0) {
|
||||
sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
|
||||
return SR_ERR;
|
||||
}
|
||||
|
||||
/*
|
||||
* 15 1 = internal test mode
|
||||
* 14 1 = external test mode
|
||||
* 13 1 = loopback test mode
|
||||
* 8-12 unused
|
||||
* 7 1 = analog mode
|
||||
* 6 1 = samplerate 400MHz
|
||||
* 5 1 = samplerate 200MHz or analog mode
|
||||
* 4 0 = logic, 1 = dso or analog
|
||||
* 2-3 unused
|
||||
* 1 0 = internal clock, 1 = external clock
|
||||
* 0 1 = trigger enabled
|
||||
*/
|
||||
v16 = 0x0000;
|
||||
if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
|
||||
v16 = 1 << 15;
|
||||
else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
|
||||
v16 = 1 << 14;
|
||||
else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
|
||||
v16 = 1 << 13;
|
||||
if (devc->dslogic_external_clock)
|
||||
v16 |= 1 << 2;
|
||||
WL16(&cfg.mode, v16);
|
||||
|
||||
v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
|
||||
WL32(&cfg.divider, v32);
|
||||
WL32(&cfg.count, devc->limit_samples);
|
||||
|
||||
len = sizeof(struct dslogic_fpga_config);
|
||||
ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
|
||||
(unsigned char *)&cfg, len,
|
||||
&transferred, 100);
|
||||
if (ret < 0 || transferred != len) {
|
||||
sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
|
||||
return SR_ERR;
|
||||
}
|
||||
|
||||
return SR_OK;
|
||||
}
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* This file is part of the libsigrok project.
|
||||
*
|
||||
* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
|
||||
* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Modified protocol commands & flags used by DSLogic */
|
||||
#define DS_CMD_GET_FW_VERSION 0xb0
|
||||
#define DS_CMD_GET_REVID_VERSION 0xb1
|
||||
#define DS_CMD_START 0xb2
|
||||
#define DS_CMD_FPGA_FW 0xb3
|
||||
#define DS_CMD_CONFIG 0xb4
|
||||
|
||||
#define DS_NUM_TRIGGER_STAGES 16
|
||||
#define DS_START_FLAGS_STOP (1 << 7)
|
||||
#define DS_START_FLAGS_CLK_48MHZ (1 << 6)
|
||||
#define DS_START_FLAGS_SAMPLE_WIDE (1 << 5)
|
||||
|
||||
enum dslogic_operation_modes {
|
||||
DS_OP_NORMAL,
|
||||
DS_OP_INTERNAL_TEST,
|
||||
DS_OP_EXTERNAL_TEST,
|
||||
DS_OP_LOOPBACK_TEST,
|
||||
};
|
||||
|
||||
struct dslogic_version {
|
||||
uint8_t major;
|
||||
uint8_t minor;
|
||||
};
|
||||
|
||||
struct dslogic_mode {
|
||||
uint8_t flags;
|
||||
uint8_t sample_delay_h;
|
||||
uint8_t sample_delay_l;
|
||||
};
|
||||
|
||||
struct dslogic_trigger_pos {
|
||||
uint32_t real_pos;
|
||||
uint32_t ram_saddr;
|
||||
uint8_t first_block[504];
|
||||
};
|
||||
|
||||
/*
|
||||
* The FPGA is configured with TLV tuples. Length is specified as the
|
||||
* number of 16-bit words, and the (type, length) header is in some
|
||||
* cases padded with 0xffff.
|
||||
*/
|
||||
#define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt)
|
||||
#define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) | 0xffff)
|
||||
#define DS_CFG_START 0xffffffff
|
||||
#define DS_CFG_MODE _DS_CFG(0, 1)
|
||||
#define DS_CFG_DIVIDER _DS_CFG_PAD(1, 2)
|
||||
#define DS_CFG_COUNT _DS_CFG_PAD(3, 2)
|
||||
#define DS_CFG_TRIG_POS _DS_CFG_PAD(5, 2)
|
||||
#define DS_CFG_TRIG_GLB _DS_CFG(7, 1)
|
||||
#define DS_CFG_TRIG_ADP _DS_CFG_PAD(10, 2)
|
||||
#define DS_CFG_TRIG_SDA _DS_CFG_PAD(12, 2)
|
||||
#define DS_CFG_TRIG_MASK0 _DS_CFG_PAD(16, 16)
|
||||
#define DS_CFG_TRIG_MASK1 _DS_CFG_PAD(17, 16)
|
||||
#define DS_CFG_TRIG_VALUE0 _DS_CFG_PAD(20, 16)
|
||||
#define DS_CFG_TRIG_VALUE1 _DS_CFG_PAD(21, 16)
|
||||
#define DS_CFG_TRIG_EDGE0 _DS_CFG_PAD(24, 16)
|
||||
#define DS_CFG_TRIG_EDGE1 _DS_CFG_PAD(25, 16)
|
||||
#define DS_CFG_TRIG_COUNT0 _DS_CFG_PAD(28, 16)
|
||||
#define DS_CFG_TRIG_COUNT1 _DS_CFG_PAD(29, 16)
|
||||
#define DS_CFG_TRIG_LOGIC0 _DS_CFG_PAD(32, 16)
|
||||
#define DS_CFG_TRIG_LOGIC1 _DS_CFG_PAD(33, 16)
|
||||
#define DS_CFG_END 0x00000000
|
||||
|
||||
struct dslogic_fpga_config {
|
||||
uint32_t sync;
|
||||
uint16_t mode_header;
|
||||
uint16_t mode;
|
||||
uint32_t divider_header;
|
||||
uint32_t divider;
|
||||
uint32_t count_header;
|
||||
uint32_t count;
|
||||
uint32_t trig_pos_header;
|
||||
uint32_t trig_pos;
|
||||
uint16_t trig_glb_header;
|
||||
uint16_t trig_glb;
|
||||
uint32_t trig_adp_header;
|
||||
uint32_t trig_adp;
|
||||
uint32_t trig_sda_header;
|
||||
uint32_t trig_sda;
|
||||
uint32_t trig_mask0_header;
|
||||
uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES];
|
||||
uint32_t trig_mask1_header;
|
||||
uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES];
|
||||
uint32_t trig_value0_header;
|
||||
uint16_t trig_value0[DS_NUM_TRIGGER_STAGES];
|
||||
uint32_t trig_value1_header;
|
||||
uint16_t trig_value1[DS_NUM_TRIGGER_STAGES];
|
||||
uint32_t trig_edge0_header;
|
||||
uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES];
|
||||
uint32_t trig_edge1_header;
|
||||
uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES];
|
||||
uint32_t trig_count0_header;
|
||||
uint16_t trig_count0[DS_NUM_TRIGGER_STAGES];
|
||||
uint32_t trig_count1_header;
|
||||
uint16_t trig_count1[DS_NUM_TRIGGER_STAGES];
|
||||
uint32_t trig_logic0_header;
|
||||
uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES];
|
||||
uint32_t trig_logic1_header;
|
||||
uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES];
|
||||
uint32_t end_sync;
|
||||
};
|
||||
|
||||
|
||||
int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
|
||||
const char *filename);
|
||||
int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
|
||||
int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
|
||||
int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
|
||||
|
|
@ -21,6 +21,7 @@
|
|||
#include <glib.h>
|
||||
#include <glib/gstdio.h>
|
||||
#include "protocol.h"
|
||||
#include "dslogic.h"
|
||||
|
||||
#pragma pack(push, 1)
|
||||
|
||||
|
|
@ -62,7 +63,7 @@ static int command_get_revid_version(struct sr_dev_inst *sdi, uint8_t *revid)
|
|||
libusb_device_handle *devhdl = usb->devhdl;
|
||||
int cmd, ret;
|
||||
|
||||
cmd = devc->dslogic ? CMD_DSLOGIC_GET_REVID_VERSION : CMD_GET_REVID_VERSION;
|
||||
cmd = devc->dslogic ? DS_CMD_GET_REVID_VERSION : CMD_GET_REVID_VERSION;
|
||||
ret = libusb_control_transfer(devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
|
||||
LIBUSB_ENDPOINT_IN, cmd, 0x0000, 0x0000, revid, 1, 100);
|
||||
|
||||
|
|
@ -107,7 +108,7 @@ SR_PRIV int fx2lafw_command_start_acquisition(const struct sr_dev_inst *sdi)
|
|||
delay = SR_MHZ(30) / samplerate - 1;
|
||||
}
|
||||
|
||||
sr_info("GPIF delay = %d, clocksource = %sMHz.", delay,
|
||||
sr_dbg("GPIF delay = %d, clocksource = %sMHz.", delay,
|
||||
(cmd.flags & CMD_START_FLAGS_CLK_48MHZ) ? "48" : "30");
|
||||
|
||||
if (delay <= 0 || delay > MAX_SAMPLE_DELAY) {
|
||||
|
|
@ -395,7 +396,7 @@ SR_PRIV void fx2lafw_receive_transfer(struct libusb_transfer *transfer)
|
|||
return;
|
||||
}
|
||||
|
||||
sr_info("receive_transfer(): status %d received %d bytes.",
|
||||
sr_dbg("receive_transfer(): status %d received %d bytes.",
|
||||
transfer->status, transfer->actual_length);
|
||||
|
||||
/* Save incoming transfer before reusing the transfer struct. */
|
||||
|
|
|
|||
|
|
@ -67,15 +67,6 @@
|
|||
#define CMD_START_FLAGS_CLK_30MHZ (0 << CMD_START_FLAGS_CLK_SRC_POS)
|
||||
#define CMD_START_FLAGS_CLK_48MHZ (1 << CMD_START_FLAGS_CLK_SRC_POS)
|
||||
|
||||
/* Modified protocol commands & flags used by DSLogic */
|
||||
#define CMD_DSLOGIC_GET_REVID_VERSION 0xb1
|
||||
#define CMD_DSLOGIC_START 0xb2
|
||||
#define CMD_DSLOGIC_CONFIG 0xb3
|
||||
#define CMD_DSLOGIC_SETTING 0xb4
|
||||
|
||||
#define CMD_START_FLAGS_DSLOGIC_STOP_POS 7
|
||||
#define CMD_START_FLAGS_DSLOGIC_STOP (1 << CMD_START_FLAGS_DSLOGIC_STOP_POS)
|
||||
|
||||
struct fx2lafw_profile {
|
||||
uint16_t vid;
|
||||
uint16_t pid;
|
||||
|
|
@ -128,6 +119,8 @@ struct dev_context {
|
|||
|
||||
/* Is this a DSLogic? */
|
||||
gboolean dslogic;
|
||||
uint16_t dslogic_mode;
|
||||
int dslogic_external_clock;
|
||||
};
|
||||
|
||||
SR_PRIV int fx2lafw_command_start_acquisition(const struct sr_dev_inst *sdi);
|
||||
|
|
@ -140,7 +133,4 @@ SR_PRIV void fx2lafw_receive_transfer(struct libusb_transfer *transfer);
|
|||
SR_PRIV size_t fx2lafw_get_buffer_size(struct dev_context *devc);
|
||||
SR_PRIV unsigned int fx2lafw_get_number_of_transfers(struct dev_context *devc);
|
||||
SR_PRIV unsigned int fx2lafw_get_timeout(struct dev_context *devc);
|
||||
|
||||
int dslogic_fpga_firmware_upload(struct libusb_device_handle *hdl,
|
||||
const char *filename);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue