sysclk-lwla: Use new trigger API.
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91fd0f7246
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bbe7e48a88
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@ -34,13 +34,20 @@ static const int32_t hwcaps[] = {
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SR_CONF_SAMPLERATE,
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SR_CONF_EXTERNAL_CLOCK,
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SR_CONF_CLOCK_EDGE,
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SR_CONF_TRIGGER_TYPE,
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SR_CONF_TRIGGER_MATCH,
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SR_CONF_TRIGGER_SOURCE,
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SR_CONF_TRIGGER_SLOPE,
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SR_CONF_LIMIT_MSEC,
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SR_CONF_LIMIT_SAMPLES,
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};
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static const int32_t trigger_matches[] = {
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SR_TRIGGER_ZERO,
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SR_TRIGGER_ONE,
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SR_TRIGGER_RISING,
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SR_TRIGGER_FALLING,
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};
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/* The hardware supports more samplerates than these, but these are the
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* options hardcoded into the vendor's Windows GUI.
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*/
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@ -402,12 +409,9 @@ static int config_set(int key, GVariant *data, const struct sr_dev_inst *sdi,
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}
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static int config_channel_set(const struct sr_dev_inst *sdi,
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struct sr_channel *ch, unsigned int changes)
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struct sr_channel *ch, unsigned int changes)
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{
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uint64_t channel_bit;
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uint64_t trigger_mask;
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uint64_t trigger_values;
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uint64_t trigger_edge_mask;
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struct dev_context *devc;
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devc = sdi->priv;
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@ -428,41 +432,6 @@ static int config_channel_set(const struct sr_dev_inst *sdi,
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devc->channel_mask &= ~channel_bit;
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}
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if ((changes & SR_CHANNEL_SET_TRIGGER) != 0) {
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trigger_mask = devc->trigger_mask & ~channel_bit;
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trigger_values = devc->trigger_values & ~channel_bit;
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trigger_edge_mask = devc->trigger_edge_mask & ~channel_bit;
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if (ch->trigger && ch->trigger[0] != '\0') {
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if (ch->trigger[1] != '\0') {
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sr_warn("Trigger configuration \"%s\" with "
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"multiple stages is not supported.",
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ch->trigger);
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return SR_ERR_ARG;
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}
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/* Enable trigger for this channel. */
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trigger_mask |= channel_bit;
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/* Configure edge mask and trigger value. */
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switch (ch->trigger[0]) {
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case '1': trigger_values |= channel_bit;
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case '0': break;
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case 'r': trigger_values |= channel_bit;
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case 'f': trigger_edge_mask |= channel_bit;
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break;
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default:
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sr_warn("Trigger type '%c' is not supported.",
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ch->trigger[0]);
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return SR_ERR_ARG;
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}
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}
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/* Store validated trigger setup. */
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devc->trigger_mask = trigger_mask;
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devc->trigger_values = trigger_values;
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devc->trigger_edge_mask = trigger_edge_mask;
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}
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return SR_OK;
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}
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@ -502,8 +471,10 @@ static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
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g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
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*data = g_variant_builder_end(&gvb);
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break;
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case SR_CONF_TRIGGER_TYPE:
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*data = g_variant_new_string(TRIGGER_TYPES);
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case SR_CONF_TRIGGER_MATCH:
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*data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
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trigger_matches, ARRAY_SIZE(trigger_matches),
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sizeof(int32_t));
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break;
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case SR_CONF_TRIGGER_SOURCE:
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*data = g_variant_new_strv(trigger_source_names,
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@ -550,6 +521,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
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sr_info("Starting acquisition.");
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devc->acquisition = acq;
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lwla_convert_trigger(sdi);
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ret = lwla_setup_acquisition(sdi);
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if (ret != SR_OK) {
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sr_err("Failed to set up acquisition.");
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@ -738,6 +738,55 @@ SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi)
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return ret;
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}
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SR_PRIV int lwla_convert_trigger(const struct sr_dev_inst *sdi)
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{
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struct dev_context *devc;
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struct sr_trigger *trigger;
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struct sr_trigger_stage *stage;
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struct sr_trigger_match *match;
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const GSList *l, *m;
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uint64_t channel_index;
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devc = sdi->priv;
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devc->trigger_mask = 0;
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devc->trigger_values = 0;
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devc->trigger_edge_mask = 0;
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if (!(trigger = sr_session_trigger_get()))
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return SR_OK;
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if (g_slist_length(trigger->stages) > 1) {
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sr_err("This device only supports 1 trigger stage.");
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return SR_ERR;
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}
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for (l = trigger->stages; l; l = l->next) {
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stage = l->data;
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for (m = stage->matches; m; m = m->next) {
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match = m->data;
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if (!match->channel->enabled)
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/* Ignore disabled channels with a trigger. */
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continue;
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channel_index = 1 << match->channel->index;
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devc->trigger_mask |= channel_index;
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switch (match->match) {
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case SR_TRIGGER_ONE:
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devc->trigger_values |= channel_index;
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break;
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case SR_TRIGGER_RISING:
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devc->trigger_values |= channel_index;
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/* Fall through for edge mask. */
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case SR_TRIGGER_FALLING:
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devc->trigger_edge_mask |= channel_index;
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break;
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}
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}
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}
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return SR_OK;
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}
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/* Select the LWLA clock configuration. If the clock source changed from
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* the previous setting, this will download a new bitstream to the FPGA.
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*/
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@ -38,7 +38,6 @@
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#define USB_TIMEOUT 3000 /* ms */
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#define NUM_CHANNELS 34
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#define TRIGGER_TYPES "01fr"
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/* Bit mask covering all 34 channels.
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*/
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@ -253,6 +252,7 @@ SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void);
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SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq);
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SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi);
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SR_PRIV int lwla_convert_trigger(const struct sr_dev_inst *sdi);
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SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi);
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SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi);
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SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi);
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