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saleae-logic16: Consolidate the samplerate limits into a single bitrate cap

This commit is contained in:
Marcus Comstedt 2016-05-18 23:10:46 +02:00
parent 41dab43ef9
commit cb193a2093
1 changed files with 2 additions and 10 deletions
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12
src/hardware/saleae-logic16/protocol.c
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@ -35,11 +35,7 @@
#define FPGA_FIRMWARE_33 "saleae-logic16-fpga-33.bitstream"
#define MAX_SAMPLE_RATE SR_MHZ(100)
#define MAX_4CH_SAMPLE_RATE SR_MHZ(50)
#define MAX_7CH_SAMPLE_RATE SR_MHZ(40)
#define MAX_8CH_SAMPLE_RATE SR_MHZ(32)
#define MAX_10CH_SAMPLE_RATE SR_MHZ(25)
#define MAX_13CH_SAMPLE_RATE SR_MHZ(16)
#define MAX_SAMPLE_RATE_X_CH SR_MHZ(300)
#define BASE_CLOCK_0_FREQ SR_MHZ(100)
#define BASE_CLOCK_1_FREQ SR_MHZ(160)
@ -596,11 +592,7 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
if (channels & (1U << i))
nchan++;
if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) ||
(nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) ||
(nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) ||
(nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) ||
(nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) {
if (nchan * samplerate > MAX_SAMPLE_RATE_X_CH) {
sr_err("Unable to sample at %" PRIu64 "Hz "
"with this many channels.", samplerate);
return SR_ERR;