saleae-logic16: Downgrade error during capture to a message.

Some clone doesn't set this to the exact same value, and both bits in 0x48 are
marked as unknown at
http://sigrok.org/wiki/Saleae_Logic16/Firmware#FPGA_variables

This fixes bug #466.
This commit is contained in:
Tim Hatch 2014-11-02 15:29:38 -08:00 committed by Uwe Hermann
parent 372c041bd8
commit cd3c4df35a
1 changed files with 2 additions and 2 deletions

View File

@ -499,8 +499,8 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
return ret; return ret;
if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) { if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) {
sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48.", reg1); sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48. "
return SR_ERR; "Proceeding anyway.", reg1);
} }
if ((ret = read_fpga_register(sdi, 10, &reg10)) != SR_OK) if ((ret = read_fpga_register(sdi, 10, &reg10)) != SR_OK)